Publications

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Abstract not provided.

Abstract not provided.

Approximately 95% of the world's integrated chips are packaged using a hot, high pressure transfer molding process. The stress created by the flow of silica powder loaded epoxy can displace the fine bonding wires and can even distort the metalization patterns under the protective chip passivation layer [l, 2]. In this study we developed a technique to measure the mechanical stress over the surface of an integrated circuit during the molding process. A CMOS test chip with 25 diffused resistor stress sensors was applied to a commercial lead frame. Both compression and shear stresses were measured at all 25 locations on the surface of the chip every 50 milliseconds during molding. These measurements have a fine time and stress resolution which should allow comparison with computer simulation of the molding process, thus allowing optimization of both the manufacturing process and mold geometry.

Unlike silicon microelectronics, photonics packaging has proven to be low yield and expensive. One approach to make photonics packaging practical for low cost applications is the use of {open_quotes}smart{close_quotes} packages. {open_quotes}Smart{close_quotes} in this context means the ability of the package to actuate a mechanical change based on either a measurement taken by the package itself or by an input signal based on an external measurement. One avenue of smart photonics packaging, the use of polysilicon micromechanical devices integrated with photonic waveguides, was investigated in this research (LDRD 3505.340). The integration of optical components with polysilicon surface micromechanical actuation mechanisms shows significant promise for signal switching, fiber alignment, and optical sensing applications. The optical and stress properties of the oxides and nitrides considered for optical waveguides and how they are integrated with micromechanical devices were investigated.

The use of commercial off-the-shelf (COTS) microelectronics for nuclear weapon applications will soon be reality rather than hearsay. The use of COTS for new technologies for uniquely military applications is being driven by the so-called Perry Initiative that requires the U.S. Department of Defense (DoD) to accept and utilize commercial standards for procurement of military systems. Based on this philosophy, coupled with several practical considerations, new weapons systems as well as future upgrades will contain plastic encapsulated microelectronics. However, a conservative Department of Energy (DOE) approach requires lifetime predictive models. Thus, the focus of the current project is on accelerated testing to advance current aging models as well as on the development of the methodology to be used during WR qualification of plastic encapsulated microelectronics. An additional focal point involves achieving awareness of commercial capabilities, materials, and processes. One of the major outcomes of the project has been the definition of proper techniques for handling and evaluation of modern surface mount parts which might be used in future systems. This program is also raising the familiarity level of plastic within the weapons complex, allowing subsystem design rules accommodating COTS to evolve. A two year program plan is presented along with test results and commercial interactions during this first year.

Multichip modules (MCMs) containing power components need a substrate with excellent heat spreading capability to both avoid hot spots and to move dissipation heat toward the system heat sinks. Polycrystalline diamond is an excellent MCM heat spreading substrate but remains several orders of magnitude too expensive and somewhat more difficult to process than conventional mother-board materials. Today`s power MCMs concentrate on moderately priced silicon wafers and aluminum nitride ceramic with their improved thermal conductivity and good thermal expansion match to power semiconductor components in comparison to traditional alumina and printed wiring board materials. However, even silicon and AlN substrates are thermally challenged by designers needs. The authors report on the integral fabrication of micro-heat pipes embedded in silicon MCM substrates (5 x 5 cm) by the use of micromachined capillary wick structures and hermetic micro-cavities. This passive microstructure results in more than a 5 times improvement in heat spreading capability of the silicon MCM substrate over a large range of power densities and operating temperatures. Thus diamond-like cooling is possible at silicon prices.

The improvements in purity of molding materials, the IC wafer passivation layers, and manufacturing quality have resulted over the last decade in extremely high reliability in commercial IC packages. In contrast the ceramic/hermetic package world is suffering from limited availability of the newest IC chips, higher cost, larger size, and decreasing quality and fewer manufacturing lines. Traditional manufacturing line qualification tests are a good start for conversion to commercial plastic parts. However, the use of standard sensitive test chips instead of product die is necessary to perform affordable, quantitative evaluations. These test chips have many integrated sensors measuring chemical, mechanical, thermal, and electrical degradation caused by manufacturing and the package environment. Besides visual, electrical test, and burn-in little has been documented on 100% nondestructive screening of plastic molded parts. Based on realistic process control and system engineer cultural expectations, user screening is necessary. Nondestructive tests of moisture and temperature excursion susceptibility are described.

Short communication.