Overview of Synthetic Aperture Radar at Sandia National Laboratories
Abstract not provided.
Abstract not provided.
Proceedings of SPIE - The International Society for Optical Engineering
High-performance radar operation, particularly Ground Moving Target Indicator (GMTI) radar modes, are very sensitive to anomalous effects of system nonlinearities. System nonlinearities generate harmonic spurs that at best degrade, and at worst generate false target detections. One significant source of nonlinear behavior is the Analog to Digital Converter (ADC). One measure of its undesired nonlinearity is its Integral Nonlinearity (INL) specification. We examine in this paper the relationship of INL to radar performance; in particular its manifestation in a range-Doppler map or image.
Typical synthetic aperture RADAR (SAR) imaging employs a co-located RADAR transmitter and receiver. Bistatic SAR imaging separates the transmitter and receiver locations. A bistatic SAR configuration allows for the transmitter and receiver(s) to be in a variety of geometric alignments. Sandia National Laboratories (SNL) / New Mexico proposed the deployment of a ground-based RADAR receiver. This RADAR receiver was coupled with the capability of digitizing and recording the signal collected. SNL proposed the possibility of creating an image of targets the illuminating SAR observes. This document describes the developed hardware, software, bistatic SAR configuration, and its deployment to test the concept of a ground-based bistatic SAR. In the proof-of-concept experiments herein, the RADAR transmitter will be a commercial SAR satellite and the RADAR receiver will be deployed at ground level, observing and capturing RADAR ground/targets illuminated by the satellite system.
Radar operation, particularly Ground Moving Target Indicator (GMTI) radar modes, are very sensitive to anomalous effects of system nonlinearities. These throw off harmonic spurs that are sometimes detected as false alarms. One significant source of nonlinear behavior is the Analog to Digital Converter (ADC). One measure of its undesired nonlinearity is its Integral Nonlinearity (INL) specification. We examine in this report the relationship of INL to GMTI performance.
Proceedings of SPIE - The International Society for Optical Engineering
A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-to-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection to host computer, parallelizing code generator, and look-up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating-point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An OpenWindows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.
This report describes the development, fabrication, and testing of a high-g piezoelectric accelerometer that uses PVF/sub 2/ as the piezoelectric transducer. The accelerometer is designed to continuously measure accelerations up to 1000,000 g. The device is packages in a 3/8'' hex head bolt and can include a built-in hybrid buffer to provide a low-output impedance analog signal. Included in this report are fabrication procedures, mechanical drawings, and software listings for test data analysis programs. 30 refs., 21 figs.