Publications

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Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately 1ns and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches. © 2008 IEEE.

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There is significant interest in forming quantum bits (qubits) out of single electron devices for quantum information processing (QIP). Information can be encoded using properties like charge or spin. Spin is appealing because it is less strongly coupled to the solid-state environment so it is believed that the quantum state can better be preserved over longer times (i.e., that is longer decoherence times may be achieved). Long spin decoherence times would allow more complex qubit operations to be completed with higher accuracy. Recently spin qubits were demonstrated by several groups using electrostatically gated modulation doped GaAs double quantum dots (DQD) [1], which represented a significant breakthrough in the solid-state field. Although no Si spin qubit has been demonstrated to date, work on Si and SiGe based spin qubits is motivated by the observation that spin decoherence times can be significantly longer than in GaAs. Spin decoherence times in GaAs are in part limited by the random spectral diffusion of the non-zero nuclear spins of the Ga and As that couple to the electron spin through the hyperfine interaction. This effect can be greatly suppressed by using a semiconductor matrix with a near zero nuclear spin background. Near zero nuclear spin backgrounds can be engineered using Si by growing {sup 28}Si enriched epitaxy. In this talk, we will present fabrication details and electrical transport results of an accumulation mode double top gated Si metal insulator semiconductor (MIS) nanostructure, Fig 1 (a) & (b). We will describe how this single electron device structure represent a path towards forming a Si based spin qubit similar in design as that demonstrated in GaAs. Potential advantages of this novel qubit structure relative to previous approaches include the combination of: no doping (i.e., not modulation doped); variable two-dimensional electron gas (2DEG) density; CMOS compatible processes; and relatively small vertical length scales to achieve smaller dots. A primary concern in this structure is defects at the insulator-silicon interface. The Sandia National Laboratories 0.35 {micro}m fab line was used for critical processing steps including formation of the gate oxide to examine the utility of a standard CMOS quality oxide silicon interface for the purpose of fabricating Si qubits. Large area metal oxide silicon (MOS) structures showed a peak mobility of 15,000 cm{sup 2}/V-s at electron densities of {approx}1 x 10{sup 12} cm{sup -2} for an oxide thickness of 10 nm. Defect density measured using standard C-V techniques was found to be greater with decreasing oxide thickness suggesting a device design trade-off between oxide thickness and quantum dot size. The quantum dot structure is completed using electron beam lithography and poly-silicon etch to form the depletion gates, Fig 1 (a). The accumulation gate is added by introducing a second insulating Al{sub 2}O{sub 3} layer, deposited by atomic layer deposition, followed by an Al top gate deposition, Fig. 1 (b). Initial single electron transistor devices using SiO{sub 2} show significant disorder in structures with relatively large critical dimensions of the order of 200-300 nm, Fig 2. This is not uncommon for large silicon structures and has been cited in the literature [2]. Although smaller structures will likely minimize the effect of disorder and well controlled small Si SETs have been demonstrated [3], the design constraints presented by disorder combined with long term concerns about effects of defects on spin decoherence time (e.g., paramagnetic centers) motivates pursuit of a 2nd generation structure that uses a compound semiconductor approach, an epitaxial SiGe barrier as shown in Fig. 2 (c). SiGe may be used as an electron barrier when combined with tensilely strained Si. The introduction of strained-Si into the double top gated device structure, however, represents additional fabrication challenges. Thermal budget is potentially constrained due to concerns related to strain relaxation. Fabrication details related to the introduction of strained silicon on insulator and SiGe barrier formation into the Sandia National Laboratories 0.35 {micro}m fab line will also be presented.

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We describe the development of a novel silicon quantum bit (qubit) device architecture that involves using materials that are compatible with a Sandia National Laboratories (SNL) 0.35 mum complementary metal oxide semiconductor (CMOS) process intended to operate at 100 mK. We describe how the qubit structure can be integrated with CMOS electronics, which is believed to have advantages for critical functions like fast single electron electrometry for readout compared to current approaches using radio frequency techniques. Critical materials properties are reviewed and preliminary characterization of the SNL CMOS devices at 4.2 K is presented.

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In this paper, we evaluate a commercially available high density plasma chemical vapor deposition (HDP-CVD) process to grow low temperature (i.e., Tin-situ & Tepitaxy < ∼460°C) germanium epitaxy for a p+-Ge/p-Si/n+-Si NIR separate absorption and multiplication avalanche photodetectors (SAM-APD). A primary concern for SAM-APDs in this material system is that high fields will not be sustainable across a highly defective Ge/Si interface. We show Ge-Si SAM-APDs that show avalanche multiplication and avalanche breakdown. A dark current of ∼0.1 mA/cm2 and a 3.2×10-4 A/W responsivity at 1310 nm were measured at punch-through. An over 400x photocurrent multiplication was demonstrated at room temperature. These results indicate that high avalanche multiplication gain is achievable in these Ge/Si heterostructures despite the highly defective interface and therefore trap assisted tunneling through the defective Ge/Si interface is not dominant at high fields. © 2007 Materials Research Society.

The silicon microelectronics industry is the technological driver of modern society. The whole industry is built upon one major invention--the solid-state transistor. It has become clear that the conventional transistor technology is approaching its limitations. Recent years have seen the advent of magnetoelectronics and spintronics with combined magnetism and solid state electronics via spin-dependent transport process. In these novel devices, both charge and spin degree freedoms can be manipulated by external means. This leads to novel electronic functionalities that will greatly enhance the speed of information processing and memory storage density. The challenge lying ahead is to understand the new device physics, and control magnetic phenomena at nanometer length scales and in reduced dimensions. To meet this goal, we proposed the silicon nanocrystal system, because: (1) It is compatible with existing silicon fabrication technologies; (2) It has shown strong quantum confinement effects, which can modify the electric and optical properties through directly modifying the band structure; and (3) the spin-orbital coupling in silicon is very small, and for isotopic pure {sup 28}Si, the nuclear spin is zero. These will help to reduce the spin-decoherence channels. In the past fiscal year, we have studied the growth mechanism of silicon-nanocrystals embedded in silicon dioxide, their photoluminescence properties, and the Si-nanocrystal's magnetic properties in the presence of Mn-ion doping. Our results may demonstrate the first evidence of possible ferromagnetic orders in Mn-ion implanted silicon nanocrystals, which can lead to ultra-fast information process and ultra-dense magnetic memory applications.

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