Publications

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Abstract not provided.

As FPGA logic density continues to increase, new techniques are needed to store initial configuration data efficiently, maintain usability, and minimize cost. In this paper, a novel compression technique is presented for Xilinx Virtex partially reconfigurable FPGAs. This technique relies on constrained hardware design and layout combined with a few simple compression techniques. This technique uses partial recon-figuration to separate a hardware design into two separate regions: a static and partial region. A bitstream containing only the static region is then compressed by removing empty frames. This bitstream will be stored in non-volatile memory and used for initialization. The remaining logic is configured through partial reconfiguration over a communication network. By applying this technique, a high level of compression was achieved (almost 90% for the V4 LX25). This compression technique requires no extra decompression circuitry and compression levels improve as device size increases. ©2009 IEEE.

Abstract not provided.

Abstract not provided.

Abstract not provided.

Packet switched data communication networks that use distributed processing architectures have the potential to simplify the design and development of new and increasingly sophisticated satellite payloads. Distributed network architectures can improve system reliability and capability and reduce size, weight, and power when compared to current architectures. This study performed a broad review of network characteristics and architectures for use on-board future satellite payloads. The concepts of topology selection, commercially available communication protocols, and architecture modeling and simulation were studied, and the results are presented in this paper. Copyright © 2008 by the American Institute of Aeronautics and Astronautics, Inc.

Emerging high-bandwidth, low-latency network technology has made network-based architectures both feasible and potentially desirable for use in satellite payload architectures. The selection of network topology is a critical component when developing these multi-node or multi-point architectures. This study examines network topologies and their effect on overall network performance. Numerous topologies were reviewed against a number of performance, reliability, and cost metrics. This document identifies a handful of good network topologies for satellite applications and the metrics used to justify them as such. Since often multiple topologies will meet the requirements of the satellite payload architecture under development, the choice of network topology is not easy, and in the end the choice of topology is influenced by both the design characteristics and requirements of the overall system and the experience of the developer.

This paper describes the design of an inverse adaptive filter, using the Least-Mean-Square (LMS) algorithm, the correct data taken with an analog filter. The gradient estimate used in the LMS algorithm is based upon the instantaneous error, e{sup 2}(n). Minimizing the mean-squared-error does not provide an optimal solution in this specific case. Therefore, another performance criterion, error power, was developed to calculate the optimal inverse model. Despite using a different performance criterion, the inverse filter converges rapidly and gives a small mean-squared-error. Computer simulations of this filter are also shown in this paper.