Neuromorphic Computing Algorithms and Architecture Research at Sandia
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Jump to search filtersA spike-Timing neuromorphic architecture
2017 IEEE International Conference on Rebooting Computing, ICRC 2017 - Proceedings
Unlike general purpose computer architectures that are comprised of complex processor cores and sequential computation, the brain is innately parallel and contains highly complex connections between computational units (neurons). Key to the architecture of the brain is a functionality enabled by the combined effect of spiking communication and sparse connectivity with unique variable efficacies and temporal latencies. Utilizing these neuroscience principles, we have developed the Spiking Temporal Processing Unit (STPU) architecture which is well-suited for areas such as pattern recognition and natural language processing. In this paper, we formally describe the STPU, implement the STPU on a field programmable gate array, and show measured performance data.
A Digital Neuromorphic Architecture Efficiently Facilitating Complex Synaptic Response Functions Applied to LSMs
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An Efficient Implementation of a LSM on the Spiking Temporal Processing Unit
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An Efficient Implementation of a Liquid State Machine on the Spiking Temporal Processing Unit
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A neurally inspired spiking temporal processing unit computational architecture
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Implementation of a Liquid State Machine with Temporal Dynamics on a Novel Spiking Neuromorphic Architecture
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Neural circuit models on emulated hardware
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Dynamic partial reconfiguration of softcore processors on the Virtex 5
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Sandia-Xilinx Virtex FPGA SEU Experiment on the International Space Station
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Partial Reconfiguration for space based applicaitons
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Hardware demonstration of high-speed networks for satellite applications
This report documents the implementation results of a hardware demonstration utilizing the Serial RapidIO{trademark} and SpaceWire protocols that was funded by Sandia National Laboratories (SNL's) Laboratory Directed Research and Development (LDRD) office. This demonstration was one of the activities in the Modeling and Design of High-Speed Networks for Satellite Applications LDRD. This effort has demonstrated the transport of application layer packets across both RapidIO and SpaceWire networks to a common downlink destination using small topologies comprised of commercial-off-the-shelf and custom devices. The RapidFET and NEX-SRIO debug and verification tools were instrumental in the successful implementation of the RapidIO hardware demonstration. The SpaceWire hardware demonstration successfully demonstrated the transfer and routing of application data packets between multiple nodes and also was able reprogram remote nodes using configuration bitfiles transmitted over the network, a key feature proposed in node-based architectures (NBAs). Although a much larger network (at least 18 to 27 nodes) would be required to fully verify the design for use in a real-world application, this demonstration has shown that both RapidIO and SpaceWire are capable of routing application packets across a network to a common downlink node, illustrating their potential use in real-world NBAs.
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