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Final Report for the Virtual Reliability Realization System LDRD

Dellin, Theodore A.; Henderson, Christopher L.; Toole, Edward J.

Current approaches to reliability are not adequate to keep pace with the need for faster, better and cheaper products and systems. This is especially true in high consequence of failure applications. The original proposal for the LDRD was to look at this challenge and see if there was a new paradigm that could make reliability predictions, along with a quantitative estimate of the risk in that prediction, in a way that was faster, better and cheaper. Such an approach would be based on the underlying science models that are the backbone of reliability predictions. The new paradigm would be implemented in two software tools: the Virtual Reliability Realization System (VRRS) and the Reliability Expert System (REX). The three-year LDRD was funded at a reduced level for the first year ($120K vs. $250K) and not renewed. Because of the reduced funding, we concentrated on the initial development of the expertise system. We developed an interactive semiconductor calculation tool needed for reliability analyses. We also were able to generate a basic functional system using Microsoft Siteserver Commerce Edition and Microsoft Sequel Server. The base system has the capability to store Office documents from multiple authors, and has the ability to track and charge for usage. The full outline of the knowledge model has been incorporated as well as examples of various types of content.

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Identification of Yield-Limiting Defects in a 0.5 Micron, Shallow Trench Isolation Technology

Henderson, Christopher L.

During the development and qualification of a radiation-hardened, 0.5 {micro}m shallow trench isolation technology, several yield-limiting defects were observed. The 256K (32K x 8) static-random access memories (SRAMs) used as a technology characterization vehicle had elevated power supply current during wafer probe testing. Many of the die sites were functional, but exhibited quiescent power supply current (I{sub DDQ}) in excess of 100 {micro}A, the present limit for this particular SRAM. Initial electrical analysis indicated that many of the die sites exhibited unstable I{sub DDQ} that fluctuated rapidly. We refer to this condition as ''jitter.'' The I{sub DDQ} jitter appeared to be independent of temperature and predominantly associated with the larger 256K SRAMs and not as prevalent in the 16K SRAMs (on the same reticle set). The root cause of failure was found to be two major processing problems: salicide bridging and stress-induced dislocations in the silicon islands.

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A Signature Analysis Method for IC Failure Analysis

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Henderson, Christopher L.

A new method of signature analysis is presented and explained. This method of signature analysis can be based on either experiential knowledge of failure analysis, observed data, or a combination of both. The method can also be used on low numbers of failures or even single failures. It uses the Dempster-Shafer theory to calculate failure mechanism confidence. The model is developed in the paper and an example is given for its use.

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The advent of failure analysis software technology

Henderson, Christopher L.

The increasing complexity of integrated circuits demands that software tools, in addition to hardware tools, be used for successful diagnosis of failure. A series of customizable software tools have been developed that organize failure analysis information and provide expert level help to failure analysts to increase their productivity and success.

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Advanced failure analysis laboratory equipment networking

Henderson, Christopher L.

Today`s integrated circuits are so complex that it is often necessary to have access to the layouts and schematics when performing voltage contrast, cross sectioning, light emission, mechanical probing, optical beam induced current, and even simple SEM and Optical Examination. To deal with these issues, Sandia National Laboratories is developing an advanced failure analysis laboratory networking scheme to provide computer control, layout navigation, schematic navigation, and report generation on each of the major pieces of failure analysis equipment. This concept is known as an Integrated Diagnostic Environment or IDE. An integrated diagnostic environment is an environment where failure analysis equipment is computer-controlled and linked by a high speed network. The network allows CAD databases to be shared between instruments, improving the failure analyst`s productivity on each analysis task. At Sandia, we are implementing this concept using SUN Sparcstation computers running Schlumberger`s IDE software. To date, we have incorporated our electron beam prober and light emission system into the environment. We will soon add our scanning optical microscope and focused ion beam system and eventually add our optical microscope and microprobe station into the network. There are a number of issues to consider when implementing an Integrated Diagnostic Environment; these are discussed in detail in this paper.

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The Behavior and Testing Implications of CMOS IC Logic Gate Open [Book Chapter]

1991, Proceedings. International Test Conference

Henderson, Christopher L.

The electrical and test properties of several logic gate open circuit defect structures were measured. Results indicate that tunneling current across fine geometry discontinuities enables low frequency operation of Integrated Circuits (ICs). No significant capacitive coupling was observed for adjacent metal interconnect or for large metal opens on the gate interconnects. These results indicate the need for different methods of open circuit defect detection during test.

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6 Results
6 Results