Publications Details
Use of air gap structures to lower intralevel capacitance
Interconnect delays, arising in part from intralevel capacitance, are one of the factors limiting the performance of advanced circuits. In addition, the problem of filling the spaces between neighboring metal lines with an insulator is becoming increasingly acute as aspect ratios increase. We address these problems simultaneously by intentionally creating an air gap between closely spaced metal lines. Undesirable topography is eliminated using a spin-on dielectric. We then cap the wafers with silicon dioxide and planarize using chemical mechanical polishing. Simple modeling of test structures predicts an equivalent dielectric constant of 1.9 on features similar to those expected for 0.25 micron technologies. Two level metal test structures fabricated in a 0.5 micron CMOS technology show that the process can be readily integrated with current standard CMOS processes. The potential problems of via misalignment, overall dielectric stack height, and the relative difficulty of ensuring void formation compared to that of ensuring a void-free fill are considered.