Publications Details
New developments in electrical linewidth and overlay metrology for ULSI fabrication processes
Compared to other metrology approaches, electrical test structures for the measurement of dimensional characteristics such as linewidth and overlay directly relate to the electrical performance of the circuits being fabricated. The inherent disadvantage of electrical techniques is that they can be applied only to the extraction of the dimensions of features patterned in electrically-conducting materials. They can not be directly applied to patterned resist films or dielectric material layers. In the case of narrow on-wafer features patterned in resist, for example, linewidths are preferably extracted by electron-beam methods. These methods are sufficiently repeatable for monitoring fabrication-process variations. However, the traceability of the units in which linewidth is expressed is thwarted by the unavailability of suitable calibration artifacts. In the case of overlay metrology, the same limitations as regards electrical conduction apply. However, similar advantages accrue in principle to electrical overlay methods when they can be utilized. It is the electrical quality of the overlay of a conducting via relative to underlying or overlying conducting material which is of driving importance for circuit functionality. This may differ from the overlay values extracted from the same patterns by commonly-used optical overlay tools. Further refinements in the state of the art in both electrical linewidth and electrical overlay metrologies are desirable as feature sizes and spacings continue to shrink in emerging generations of devices. This paper discusses some recent innovations which have been recently introduced and indicates new roles for electrical metrology in low-cost certification of reference materials for both linewidth and overlay applications.