Publications Details
High voltage considerations for Silicon-on-Insulator devices using porous silicon
We describe a Silicon-on-Insulator (SOI) structure for high voltage BICMOS uniquely suited to the use of porous silicon (PS). In this SOI structure, bulk, high speed bipolar devices are readily integrated with CMOS high voltage and logic devices (smart power). To investigate the processing compatibility of PS with this structure, we measured breakdown strength and etch rate of thermally treated PS in 7:1 buffered oxide etch (BOE) and determined that they can approach values typical of thermal silicon oxides/nitrides. 7 refs., 2 figs.