Publications Details
Analysis of Interlayer Shorts in a 0.5 {micro}m CMOS IC Technology
Sandia is manufacturing CMOS ICs with 0.5 {micro}m LOCOS and shallow trench isolation (STI) technologies and is developing a 0.35 {micro}m SOI technology. A program based on burn-in and life tests is being used to qualify the 0.5 {micro}m technologies for delivery of high reliability ICs to customers for military and space applications. Representative ICs from baseline wafer lots are assembled using a high reliability process with multilayer hermetic, ceramic packages. These ICs are electrically tested before, during, and after burn-in and subsequent 1000 hour dynamic and static life tests. Two types of ICS are being used for this qualification, a 256K bit SRAM and a Microcontroller Core (MCC). Over 600 ICs have successfully completed these qualification tests, resulting in a failure rate estimate of less than 4 FITS for satellite applications. Recently, a group of SRAMS from a development wafer lot incorporating nonqualified processes of the 0.5 {micro}m LOCOS technology had an unusually high number of failures during the initial electrical test after packaging. The investigation of these failures is described.