Hole and electron trapping in irradiated MOS devices
Short communication.
Short communication.
IEEE Transactions on Nuclear Science
We present a method to conservatively estimate MOS hardness in space that shares the same technical basis as MIL-STD 883C, Test Method 1019.4, but permits greater latitude in part selection for low-dose space systems. Cobalt-60 irradiation at 50–300 rad(Si)/s followed by 25°C anneal is shown to provide an effective test of oxide-charge related failures at low dose rates that is considerably less conservative than Method 1019.4. For MOS devices with gate oxides thinner than 100 nm, we show that an elevated temperature “rebound test” generally is not required for systems with total dose requirements less than 5 krad(Si). For thicker gate oxides and/or higher-dose system requirements, rebound testing per Method 1019.4 generally is required to ensure that devices do not fail in space due to interface-trap effects. © 1991 IEEE
It is shown that preirradiation channel-mobility and 1/f-noise measurements can reveal a great deal about postirradiation interface- and oxide-trap charge buildup in MOS transistors. A model is developed to explain the observed correlations. 10 refs., 4 figs.
In actual circuit application, MOS transistor bias is generally not constant through radiation exposure. Nevertheless, the overwhelming majority of radiation effects studies and hardness assurance testing is performed at constant bias for simplicity and practicality. In the past 15 years, however, it has been shown that oxide- and interface-trap charge buildup and annealing during switched-bias exposures can differ quantitatively and qualitatively from that observed during steady-state exposures. This has made it difficult to develop predictive models of MOS circuit response for actual use conditions, and has introduced uncertainty into hardness assurance testing of MOS circuits. In this summary, defect growth and annealing rates are compared for steady-state and switched-biased irradiations of MOS transistors. A simple method is described to predict MOS oxide-trap charge, interface-trap charge, and mobility degradation during switched-bias exposures from steady-state ( on'' and off'') irradiations. Over a wide range of switching conditions for the devices examined, this method has provided predictions typically accurate to within better than 20%. The maximum error observed to data is less than 40%. This method should allow the total-dose radiation response of MOS circuits in real-use scenarios to be modeled with improved accuracy and flexibility. 9 refs., 3 figs.
Lot acceptance tests are evaluated for nonhardened CMOS devices for low total-dose space applications. Examples are presented for cases in which gate- or field-oxide leakage dominates device response. 12 refs., 3 figs.
It is shown how standard ..delta..Vth and mobility measurements made on otherwise identical n- and p-channel transistors can be combined to accurately estimate radiation-induced ..delta..V/sub ot/ and ..delta..V/sub it/. Applications of the method are described. 12 refs., 2 figs.
We find a strong correlation between the preirradiation 1/f noise of pMOS transistors and their radiation hardness. This suggests that current fluctuations may provide a useful, nondestructive probe of defects in MOS devices. 18 refs., 4 figs., 1 tab.