Publications

Convergent lines of evidence are reviewed which show that near-interfacial oxide traps (border traps) that exchange charge with the Si can strongly affect the performance, radiation response, and long-term reliability of MOS devices. Observable effects of border traps include capacitance-voltage (C-V) hysteresis, enhanced 1/f noise, compensation of trapped holes, and increased thermally stimulated current in MOS capacitors. Effects of faster (switching times between ∼10-6 s and ∼1 s) and slower (switching times greater than ∼1 s) border traps have been resolved via a dual-transistor technique. In conjunction with studies of MOS electrical response, electron paramagnetic resonance and spin dependent recombination studies suggest that E' defects (trivalent Si centers in SiO2 associated with O vacancies) can function as border traps in MOS devices exposed to ionizing radiation or high-field stress. Hydrogen-related centers may also be border traps. © 1996 IEEE.

A first-principles approach to radiation hardness assurance was described that provides the technical background to the present US and European total-dose radiation hardness assurance test methods for MOS technologies, TM 1019.4 and BS 22900. These test methods could not have been developed otherwise, as their existence depends not on a wealth of empirical comparisons of IC data from ground and space testing, but on a fundamental understanding of MOS defect growth and annealing processes. Rebound testing should become less of a problem for advanced MOS small-signal electronics technologies for systems with total dose requirements below 50--100 krad(SiO{sub 2}) because of trends toward much thinner gate oxides. For older technologies with thicker gate oxides and for power devices, rebound testing is unavoidable without detailed characterization studies to assess the impact of interface traps on devices response in space. The QML approach is promising for future hardened technologies. A sufficient understanding of process effects on radiation hardness has been developed that should be able to reduce testing costs in the future for hardened parts. Finally, it is hoped that the above discussions have demonstrated that the foundation for cost-effective hardness assurance tests is laid with studies of the basic mechanisms of radiation effects. Without a diligent assessment of new radiation effects mechanisms in future technologies, one cannot be assured that the present generation of radiation test standards will continue to apply.

In this paper we apply a ``dual-transistor border-trap`` (DTBT) technique that combines high-frequency charge-pumping and lower-frequency threshold-voltage measurements to estimate bulk-oxide-trap, interface-trap, and border-trap densities in irradiated MOS transistors. This method takes advantage of the different time scales in which interface traps and border traps exchange charge with the Si to obtain an estimate of the density of faster border traps often mistaken for interface traps. Effects of slower border traps are also inferred from changes in the ``bulk`` oxide-trap charge density through switched-bias annealing. To our knowledge, this is the first time fast and slow border-trap effects have been separated quantitatively in MOS devices. Possible microstructures for fast and slow border traps are suggested.

MOS oxides have been fabricated by oxidation of silicon in N{sub 2}O. Processes studied include oxidation in N{sub 2}O alone, and two-step oxidation in O{sub 2} followed by N{sub 2}O. For both oxides, a nitrogen-rich layer with a peak N concentration of {approximately} 0.5 at. % is observed at the Si-SiO{sub 2} interface with SIMS. Electrical characteristics of N{sub 2}O oxides, such as breakdown and defect generation, are generally improved, especially for the two-step process. Drawbacks typically associated with NH{sub 3}-nitrided oxides such as high fixed oxide charge and enhanced electron trapping, are not observed in N{sub 2}O oxides, which is probably due to their smaller nitrogen content.

Thermally-stimulated-current and capacitance-voltage measurements reveal enhanced hole trapping in bipolar spacer-oxide capacitors irradiated at 0 V at low dose rates. Possible mechanisms and implications for bipolar low-rate response are discussed.

The correlation of hot carrier stress and ionization induced gain degradation in npn BJTs was studied to determine if hot-carrier stress could be used as a hardness assurance tool for total dose. The correlation was measured at the wafer level and for several hardening variations for a single process technology. Additional experiments are planned and will be presented in the full paper. Based on a detailed physical analysis of the mechanisms for hot-carrier stress and ionization no correlation was expected. The results demonstrated the lack of correlation and indicate that hot-carrier stress degradation is not a predictor of total dose response.

A simple method to estimate the threshold-voltage shift in MOSFETs due to low-dose-rate ionizing irradiation based on MIL-STD-883D Method 1019.4 is demonstrated. The realm of applicability of this approach is explored.

The excess base current in an irradiated BJT increases superlinearly with total dose at low-total-dose levels. In this regime, the excess base current depends on the particular charge-trapping properties of the oxide that covers the emitter base junction. The device response is dose-rate-, irradiation-bias-, and technology-dependent in this regime. However, once a critical amount of charge has accumulated in the oxide, the excess base current saturates at a value that is independent of how the charge accumulated. This saturated excess base current depends on the device layout, bulk lifetime in the base region, and the measurement bias. In addition to providing important insight into the physics of bipolar-transistor total-dose response, these results have significant circuit-level implications. For example, in some circuits, the transistor gain that corresponds to the saturated excess base current is sufficient to allow reliable circuit operation. For cases in which the saturated value of current gain is acceptable, and where other circuit elements permit such over-testing, this can greatly simplify hardness assurance for space applications. © 1994 IEEE

Oxynitrides have been grown by oxidation in N2O in a standard thermal oxidation furnace. Two N2O processes have been studied: Oxidation in N2O only, and two-step oxidation with initial oxidation in O2 followed by oxidation/nitridation in N2O. Results are presented for radiation damage at 80 and 295K, hole trapping, interface trap creation, electron spin resonance, and hole detrapping using thermally-stimulated current analysis. N2O oxydo not appear to have the well-known drawbacks of NH3-annealed oxynitrides. Creation of interface traps during irradiation is reduced in the N2O oxynitrides, with the degree of improvement depending on the fabrication process. © 1994 IEEE

The role of net positive oxide trapped charge and surface recombination velocity on excess base current in BJTs is identified. The effects of the two types of damage can be detected by plotting the excess base current versus base-emitter voltage. Differences and similarities between ionizing-radiation-induced and hot electron-induced degradation are discussed.

Nitrided gate oxides have been fabricated by furnace oxidation in N{sub 2}O with and without prior oxidation in O{sub 2}. SIMS nitrogen profiles show a sharp peak at the Si-insulator interface for both processes. Improved breakdown characteristics and reduced oxide damage after irradiation and charge injection are obtained.

Recent work has shown that near-interfacial oxide traps that communicates with the underlaying Si (``border traps``) can play a significant role in determining MOS radiation response and long-term reliability. Thermally-stimulated-current 1/f noise, and frequency-dependent charge-pumping measurements have been used to estimate border-trap densities in MOS structures. These methods all require high-precision, low-noise measurements that are often difficult to perform and interpret. In this summary, we describe a new dual-transistor method to separate bulk-oxide-trap, interface-trap, and border-trap densities in irradiated MOS transistors that requires only standard threshold-voltage and high-frequency charge-pumping measurements.

Damage induced during electron-beam metallization results in a three-order-of-magnitude increase in the generation rate of bulk GaAs. The damage appears to be radiation induced, with low-energy electrons being the most likely from p{sup +}-i-n-i-p{sup +}-GaAs layers damaging mechanism.

The effects of the midgap-level interface trap density and net oxide charge on the total-dose gain degradation of a bipolar transistor are separately identified. The superlinear dose dependence of the excess base current is explained.

Qualitatively different trends in postirradiation electrical response are observed in MOS devices after very long (up to 2.75-year) switched-bias bakes. A revised defect nomenclature is introduced, and implications for MOS defect models are discussed.

MOSFETs historically have exhibited large 1/f noise magnitudes because of carrier-defect interactions that cause the number of channel carriers and their mobility to fluctuate. Uncertainty in the type and location of defects that lead to the observed noise have made it difficult to optimize MOSFET processing to reduce the level of 1/f noise. This has limited one`s options when designing devices or circuits (high-precision analog electronics, preamplifiers, etc.) for low-noise applications at frequencies below {approximately}10--100 kHz. We have performed detailed comparisons of the low-frequency 1/f noise of MOSFETs manufactured with radiation-hardened and non-radiation-hardened processing. We find that the same techniques which reduce the amount of MOSFET radiation-induced oxide-trap charge can also proportionally reduce the magnitude of the low-frequency 1/f noise of both unirradiated and irradiated devices. MOSFETs built in radiation-hardened device technologies show noise levels up to a factor of 10 or more lower than standard commercial MOSFETs of comparable dimensions, and our quietest MOSFETs show noise magnitudes that approach the low noise levels of JFETS.

Different hardness-assurance tests are often required for advanced bipolar devices than for CMOS devices. In this work, the dose-rate dependence of bipolar current-gain degradation is mapped over a wide range of dose rates for the first time, and it is very different from analogous MOSFET curves. Annealing experiments following irradiation show negligible change in base current at room temperature, but significant recovery at temperatures of 100°C and above. In contrast to what is observed in MOSFET’s, irradiation and annealing tests cannot be used to predict the low-dose-rate response of bipolar devices. A comparison of x-ray-induced and 60Co gamma-ray-induced gain degradation is reported for the first time for bipolar transistors. The role of the emitter bias during irradiation is also examined. Implications for hardening and hardness assurance are discussed. © 1993 IEEE

There is a discrepancy between literature estimates of trapped-hole energies in irradiated SiO{sub 2} obtained via thermal and optical methods (0.6-1.4 eV and 3 eV, respectively). A method has been developed for obtaining an improved estimate of the energy distribution of trapped holes in irradiated SiO{sub 2}, which brings thermal and optical estimates into much closer agreement. Experimental and theoretical TSC (thermally stimulated current) spectra are shown for a soft MOS capacitor with a 350-nm oxide cycled through 4 irradiations (10 keV x rays) and TSC measurements. Four trap-energy distributions were also independently derived from TSC at different ramp rates for a 45-nm radiation-hardened oxide. The trap distributions inferred from TSC for the 45-nm hard oxide agree with each other and with that inferred for the soft 350-nm oxide. 2 figs, 8 refs. (DLC)

A revised nomenclature for defects in MOS devices is described which clearly distinguishes the language used to describe the physical location of defects from that used to describe their electrical response. ''Oxide traps'' are simply defects in the SiO{sub 2} layer, and ''interface traps'' are defects at the Si/SiO{sub 2} interface; nothing is presumed about how either communicates with the underlying Si. ''Fixed states'' are defined electrically as trap levels that do not communicate with the Si on the time scale, but ''switching states'' can exchange charge with the Si. Fixed states presumably are oxide traps, but switching states can either be interface traps or near-interfacial oxide traps that can communicate with the Si, i.e. ''border traps.'' Thus the term ''traps'' is reserved for defect location, and the term ''states'' for electrical response. This defect picture is used to provide new insight into the response of MOS capacitors with 45-nm radiation-hardened oxides to electrical stress and annealing; capacitance-voltage and thermally-stimulated-current measurements are used. 2 figs, 14 refs. (DLC)

An analytic model with no free parameters has been developed which accurately describes thermally-stimulated-current (TSC) measurements spanning more than a factor of 50 in average heating rate. The model incorporates Schottky electric-field-induced barrier lowering and a temperature-dependent “attempt-to-escape frequency” equal to ∼1014 Hz at 300°C. Applying this model to TSC measurements provides significantly improved estimates of the energy distribution of trapped holes in irradiated SiO2. All devices examined, including soft and (wet and dry) hard oxides from five process technologies, show similar energy distributions, with a minor peak at ∼1.2 eV and a broad major peak centered ∼1.7-2.0 eV above the SiO2 valence band. These energies are closer to photoinjection and tunneling estimates of trapped-hole energy in the literature than previous estimates based on TSC or thermal annealing. We also find that the trapped-electron density in irradiated SiO2 is proportional to the trapped-hole density over a wide range of irradiation conditions. Both the trapped-hole and trapped-electron densities scale with the applied oxide electric field (Eox) during irradiation as ∼(Eox)-1/2. These results strongly support the idea that electrons are trapped at sites associated with trapped holes. Wet gate oxides are found to trap significantly fewer electrons per trapped hole (∼16%) than dry oxides (∼48%), suggesting that, on average, holes may be trapped closer to the Si/SiO2 interface in the dry oxides than in the wet oxides. Possible models of the trapped-hole/trapped-electron complex are described, and implications for device long-term reliability and annealing response are discussed. © 1992 IEEE

It is shown that preirradiation channel-mobility and 1/f-noise measurements can reveal a great deal about postirradiation interface- and oxide-trap charge buildup in MOS transistors. A model is developed to explain the observed correlations. 10 refs., 4 figs.

We present a method to conservatively estimate MOS hardness in space that shares the same technical basis as MIL-STD 883C, Test Method 1019.4, but permits greater latitude in part selection for low-dose space systems. Cobalt-60 irradiation at 50–300 rad(Si)/s followed by 25°C anneal is shown to provide an effective test of oxide-charge related failures at low dose rates that is considerably less conservative than Method 1019.4. For MOS devices with gate oxides thinner than 100 nm, we show that an elevated temperature “rebound test” generally is not required for systems with total dose requirements less than 5 krad(Si). For thicker gate oxides and/or higher-dose system requirements, rebound testing per Method 1019.4 generally is required to ensure that devices do not fail in space due to interface-trap effects. © 1991 IEEE

Short communication.

In actual circuit application, MOS transistor bias is generally not constant through radiation exposure. Nevertheless, the overwhelming majority of radiation effects studies and hardness assurance testing is performed at constant bias for simplicity and practicality. In the past 15 years, however, it has been shown that oxide- and interface-trap charge buildup and annealing during switched-bias exposures can differ quantitatively and qualitatively from that observed during steady-state exposures. This has made it difficult to develop predictive models of MOS circuit response for actual use conditions, and has introduced uncertainty into hardness assurance testing of MOS circuits. In this summary, defect growth and annealing rates are compared for steady-state and switched-biased irradiations of MOS transistors. A simple method is described to predict MOS oxide-trap charge, interface-trap charge, and mobility degradation during switched-bias exposures from steady-state ( on'' and off'') irradiations. Over a wide range of switching conditions for the devices examined, this method has provided predictions typically accurate to within better than 20%. The maximum error observed to data is less than 40%. This method should allow the total-dose radiation response of MOS circuits in real-use scenarios to be modeled with improved accuracy and flexibility. 9 refs., 3 figs.

Lot acceptance tests are evaluated for nonhardened CMOS devices for low total-dose space applications. Examples are presented for cases in which gate- or field-oxide leakage dominates device response. 12 refs., 3 figs.