Reconfigurable computing aspects of the Cray XD1
Abstract not provided.
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Jump to search filtersReconfigurable computing aspects of the Cray XD1
Abstract not provided.
Network intrusion detection systems on FPGAs with onchip network interfaces
Proposed for publication in the International Journal of Electronics.
Abstract not provided.
A network interface for enabling visualization with FPGAs
Visualization in scientific computing refers to the process of transforming data produced by a simulation into graphical representations that help scientific users interpret the results. While the back-end rendering phase of this work can be performed efficiently in graphics card hardware, the front-end 'post processing' portion of visualization is currently performed entirely in software. Field-Programmable Gate Arrays (FPGAs) are an attractive option for accelerating post-processing operations because they enable users to offload computations into reconfigurable hardware. A key challenge in utilizing FPGAs for this work is developing an infrastructure that allows FPGAs to be integrated into a distributed visualization system. We propose a networked approach, where each post-processing FPGA is equipped with specialized network interface (NI) hardware that is capable of transporting graphics commands across the network to existing rendering resources. In this paper we discuss a NI for FPGAs that is comprised of a Chromium OpenGL interface, a TCP Offload Engine, and a Gigabit Ethernet module. A prototype system has been tested for a distributed isosurfacing application.
Network intrusion detection systems on FPGAs with on-chip network interfaces
Abstract not provided.
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