Publications

During the 1980s Sandia designed, developed, fabricated, tested, and delivered hundreds of thousands of radiation hardened Integrated Circuits (IC) for use in weapons and satellites. Initially, Sandia carried out all phases, design through delivery, so that development of next generation ICs and production of current generation circuits were carried out simultaneously. All this changed in the mid-eighties when an outside contractor was brought in to produce ICs that Sandia developed, in effect creating a crisp separation between development and production. This partnership had a severe impact on operations, but its more damaging effect was the degradation of Sandia`s microelectronics capabilities. This report outlines microelectronics development and production in the early eighties and summarizes the impact of changing to a separate contractor for production. This record suggests that low volume production be best accomplished within the development organization.

An overview of the operations of Sandia`s Microelectronics Development Lab (MDL) is to develop radiation hardened IC, but techniques used for IC processing have been applied to a variety of related technologies such as micromechanics, smart sensors, and packaging.

Integrated circuit logic states are maintained by virtue of specific transistor combinations being either on'' (conducting) or off'' (nonconducting). High energy ion strikes on the microcircuit generate photocurrents whose primary detrimental effect is to make off'' transistors appear on,'' confusing the logic state and leading to single event upset (SEU). Protection against these soft errors is accomplished using either technology or circuit techniques, actions that generally impact yield and performance relative to unhardened circuits. We describe, and using circuit simulations analyze, a technique for hardening latches which requires combinations of technology and circuit modifications, but which provides SEU immunity without loss of speed. Specifically, a single logic state is hardened against SEU using technology methods and the information concerning valid states is then used to simplify hardened circuit design. The technique emphasizes some basic hardening concepts, ideas for which will be reviewed. 3 refs., 2 figs.