Publications Details
I{sub DDQ} testing for ultimate low power design verification and defect detection
I{sub DDQ} testing is mandatory to ensure that low power CMOS ICs meet their design intent. I{sub DDQ} testing is both a design verifier for low quiescent current and a sensitive production test for defects. Quiescent power reduction is particularly important for products such as cardiac pacemakers, laptop computers, and cellular telephones.