Publications Details
Integration of thin film decoupling capacitors
Thin film decoupling capacitors consisting of submicron thick, sol-gel Pb(Zr,Ti)O{sub 3} layers between Pt electrodes on a Si substrate have recently been developed. Because the capacitor structure needs to be only {approximately}3 {mu}m thick, these devices offer advantages such as decreased package volume and ability to integrate so that interconnect inductance is decreased, which allows faster IC processing rates. To fully utilize these devices, techniques of integrating them onto packages such as multi-chip modules and printed wiring boards or onto IC dies must be developed. The results of our efforts at developing integration processes for these capacitors are described here. Specifically, we have demonstrated a process for printing solder on the devices at the Si wafer level and reflowing it to form bumps and have developed a process for fabricating the devices on thin (25 to 75 {mu}m) substrates to facilitate integration onto ICs and printed wiring boards. Finally, we assessed the feasibility of fabricating the devices on rough surfaces to determine whether it would be possible to fabricate these capacitors directly on multi-layer ceramic substrates.