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CMOS IC I sub DDQ testing for the 1990s
Significant improvements in CMOSIC quality, reliability, and fabrication yield can be readily achieved in the 1990s by appropriate implementation of tests for quiescent power supply current (I{sub DDQ}). As part of an overall quality management program, I{sub DDQ} testing incorporated with design for testability and modified conventional logic response testing enables 100% stuck-at fault coverage, quality improvement goals of defective levels less than 100 PPM, and reliability greater than 0.999 for 30 years. 9 refs., 2 figs., 1 tab.