Publications Details

An alternative approach to filled--via processing

Farino, A.J.

In order to create sub micron vias between metal layers on silicon IC circuits, the tungsten filled via processes have been in a constant state of development over the past 15 years. Processing is complex, expensive, and difficult to reproduce. The introduction of galvanic cells, via undercutting, and exposed plugs are just some of the plagues that have hit several users of the technology. Discussed in this paper is an alternative approach to the complex tungsten filled via interconnect process. The proposed process yields well at sub micron geometries, is easy to perform, and is inexpensive compared to the tungsten filled via process. Contact resistance improves greatly over the standard tungsten process. The test run achieved a mean value of 0.25 ohms per via compared to historic tungsten process that yields 0.4 ohms per via. The distribution was also excellent with sigma recorded at 0.025 ohms per via.