Ultra-Wide-Bandgap Semiconductors for Generation-After-Next Power Electronics
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We have examined ground faults in PhotoVoltaic (PV) arrays and the efficacy of fuse, current detection (RCD), current sense monitoring/relays (CSM), isolation/insulation (Riso) monitoring, and Ground Fault Detection and Isolation (GFID) using simulations based on a Simulation Program with Integrated Circuit Emphasis SPICE ground fault circuit model, experimental ground faults installed on real arrays, and theoretical equations.
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The continued exponential growth of photovoltaic technologies paves a path to a solar-powered world, but requires continued progress toward low-cost, high-reliability, high-performance photovoltaic (PV) systems. High reliability is an essential element in achieving low-cost solar electricity by reducing operation and maintenance (O&M) costs and extending system lifetime and availability, but these attributes are difficult to verify at the time of installation. Utilities, financiers, homeowners, and planners are demanding this information in order to evaluate their financial risk as a prerequisite to large investments. Reliability research and development (R&D) is needed to build market confidence by improving product reliability and by improving predictions of system availability, O&M cost, and lifetime. This project is focused on understanding, predicting, and improving the reliability of PV systems. The two areas being pursued include PV arc-fault and ground fault issues, and inverter reliability.
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IEEE International Reliability Physics Symposium Proceedings
A method for extracting interface trap density (DIT) from subthreshold I-V characteristics is used to analyze data on a SiC MOSFET stressed for thirty minutes at 175°C with a gate bias of-20 V. Without knowing the channel doping, the change in DIT can be calculated when referenced to an energy level correlated with the threshold voltage. © 2014 IEEE.
IEEE International Reliability Physics Symposium Proceedings
A method for extracting interface trap density (DIT) from subthreshold I-V characteristics is used to analyze data on a SiC MOSFET stressed for thirty minutes at 175°C with a gate bias of-20 V. Without knowing the channel doping, the change in D
IEEE International Reliability Physics Symposium Proceedings
A method for extracting interface trap density (DIT) from subthreshold I-V characteristics is used to analyze data on a SiC MOSFET stressed for thirty minutes at 175°C with a gate bias of-20 V. Without knowing the channel doping, the change in DIT can be calculated when referenced to an energy level correlated with the threshold voltage. © 2014 IEEE.