Publications Details

Efficient wiring of reconfigurable parallel processors

Greenberg, D.S.

The advent of chips which include one or more CPUS, some local memory, and rudimentary communications and routing hardware has opened a new area in computer architecture design. What is the best way to connect these chips to solve particular problems? This paper defines the efficiency of a wiring scheme for a set of communication patterns. It then gives upper and lower bounds on the best efficiency achievable. It also presents simple wiring schemes for some stencil patterns used in mesh-based discrete simulations.