Publications Details

A proposed SEU tolerant DRAM cell

Agrawal, G.R.

A novel DRAM cell technology consisting of an access transistor and a bootstrapped storage capacitor with an integrated breakdown diode is proposed. This design offers considerable resistance to single event cell hits. The information change packet is shielded from an SE hit by placing the vulnerable node in a self-compensating standby state. The proposed cell is comparable in size to a conventional DRAM cell, but simulations show an improvement in critical charge of two orders of magnitude.