Sandia’s Microelectronics Commons Partnerships and Capabilities

Sandia’s Microsystems Engineering, Science, and Applications (MESA) complex integrates the numerous scientific disciplines necessary to produce functional, robust, integrated microsystems and represents the center of Sandia’s investment in microsystems research, development, and prototyping activities.

Sandia is a core partner of the DOD Microelectronics Commons (MEC). Microelectronics Commons Hubs across the country aimed creating a direct pathway to reduce the country’s reliance on foreign microelectronics and safeguard the nation from supply chain risks. With a large footprint in microelectronics, Sandia’s capabilities span multiple MEC thrust areas.

One of the key capabilities at Sandia is the MESA complex. This complex is comprised of a 200mm silicon fab, a 100mm compound semiconductor fab, an advanced packaging facility, and approximately 100 microelectronics laboratories. MESA manufactures and qualifies dozens of different rad-hard products for National Security applications in an ITAR environment, while concurrently supporting a robust portfolio of leading-edge R&D programs. MESA’s agile, high work mix, low volume fabs are especially proficient in semiconductor technology maturation (TRL 3 to TRL 6). ​

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Sandia also co-manages the Center for Integrated Nanotechnologies (CINT), a Department of Energy nanoscience user facility. MESA and CINT are U.S. National Laboratory resources that partner extensively with academia, industry, and government entities, support multi-project wafer runs, and contribute key capabilities to the DoD Microelectronics Commons SWAP hub. 

Sandia capabilities can be accessed by partnering with Sandia staff on R&D projects or by submitting a user proposal to CINT to conduct research on-site at CINT.

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Capability Partner and Member
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Sandia’s Microelectronics Capabilities

  • CMOS Full Flow Production (ITAR): 350nm, 180nm​
  • DMEA Trusted Foundry ​
  • Custom ASIC PDKs (ITAR)​
  • MEMS (Microelectromechanical Systems) full flows ​
  • Multiferroic Materials, including AlN, ScAlN, Magnetics ​
  • Silicon Photonics full flows​
  • HI lasers and TFLN​
  • Quantum Ion Trap Foundry​
  • In-Line Wafer Probe and Electrical Parameter Testing​
  • State-of-the-Art Integrated Circuit Design
  • Epitaxy: GaAs, InP, GaN, GaSb across MOCVD and MBE​
  • 100 mm Full flow UWBG AlGaN HEMTS & diodes*​
  • Full flows in GaN, GaAs, InP, and GaSb platforms​
  • VCSELs, HBTs, detectors, small scale integrated circuits, lasers​
  • InP Photonic Integrated Circuit Multi-project wafer with PDK​
  • Full flow production Packaging for ASICs and power electronics including Plastic Ball Grid Arrays (PBGA) and ceramic leadless chip carriers (CLCC). ​
  • Heterogeneous Integration​
  • C4, SnAg/Cu Pillar, and gold pillar integration​
  • Thermocompression flip chip bonding (Die-to-Wafer and Die-to-Die)​
  • Cu/SiO2 hybrid integration and hybrid bonding​
  • Direct bonding (Wafer-to-Wafer)​
  • Indium bump integration and bonding​
  • Through Silicon via (TSV) integration, back thinning, and reveal​
  • Die level processing available for most processes
  • Burn-In ​
  • Environmental Testing ​
  • Radiation Testing ​
  • Failure Analysis ​
  • RF Testing up to 150 GHz ​
  • Advanced Metrology and Characterization Capability