Fabrication, Testing and Validation Capabilities

Sandia’s ASIC development team develops and maintains digital, analog, and mixed-signal design expertise along with a deep understanding of technology offerings and design methodologies to provide custom microelectronic products and engineering services that fulfill the diverse needs of our customers. We focus on developing unique, high reliability custom solutions for high consequence applications.

We have strong partnerships with both our in-house MESAFab to provide mixed-signal, radiation-hardened, low-volume, application-specific integrated circuit (ASIC) products and other Trusted Foundries, enabling us to provide mixed-signal, high-performance, and high-density system-on-chip (SoC) solutions at leading edge technologies.

Sandia’s unique application driven solutions include:

• Security-based Application-Specific Integrated Circuits (ASICs)
• Secure Microprocessors
• Secure Interfaces
• Trusted Design

• High-consequence, High-reliability ICs – ICs that cannot fail
• High-performance ICs
• Low-noise Analog Electronics Designs
• Low-power and Asynchronous Designs
• Sensor Readout Electronics (e.g. ROIC)
• MEMS Interface Electronics
• Silicon, Optical, and Nano Technology Integration
• Special Processor/accelerator Architecture and Designs
• Fast-turn, Radiation-Hardened Structured ASIC
• Intellectual Property Development
• System Modeling

Combining our ASIC solutions with our other in-house capabilities in fabrication, packaging, and test, failure analysis, and reliability, Sandia can offer a total integrated circuit design solution.

Sandia’s Multi-Project Wafer (MPW) Program provides MPW services for radiation-hardened Application-Specific Integrated Circuits (ASICs).

MPW services integrate a number of different integrated circuit designs on a single reticle set. Sharing mask and wafer resources reduces the overall cost per design and makes it more cost effective to produce integrated circuits in low quantities.

Sandia National Laboratories’ Multi-Project Wafer Program offers access to its Trusted Design Center and high-reliability ASIC production facility. The program includes engineering support for MPW design, technology, fabrication, test and packaging, all in a trusted environment.

The MPW Program will be available to external customers beginning in 2010.

Program features include:
• Strategic radiation-hardened 3.3V, 0.35μm mixed-signal CMOS-SOI technology.
• Resistors, MIM capacitors, and diode passives.
• Standard Cells and IOs.
• Library of common digital and analog elements.
• Cadence Process-Design Kit.

Sandia National Laboratories’ structured Application Specific Integrated Circuit (ASIC) provides a radiation-hardened, via-configurable implementation platform with ASIC-like performance. Structured ASICs enable rapid turn-around, lower Non-Recurring Engineering (NRE) and development costs. Pre-qualified base arrays reduce development risk, while open architecture minimizes Diminishing Manufacturing Sources (DMS) issues. Enables safe, secure, user-defined trusted hardware, and the regular, fabric-like structure enhances verifiability of trusted parts.

Special Features

• Metal-via configurable, fabric-like structure using ViASIC™ ViaMask Technology.
• Four Power-Quadrants with specialized interface circuits that allow up to four independent power supplies for power sequencing and redundancy operations.
• Unused transistors and circuits are isolated from power and ground to minimize power consumption, static current and photocurrent.
• On-package decoupling capacitors.

Applications include:

• Command & Control
• Instrumentation
• Sensor Monitoring
• Obsolescent Parts & FPGA Emulation
• Rad-hard environment operations
• High-Reliability Systems

Sandia National Laboratories has historically focused on high-reliability custom solutions for high-consequence applications. Today Sandia is a DoD Category 1A Accredited Supplier of both "trusted design and foundry services” optimized for high-mix low-volume custom radiation-hardened, digital, analog and mixed-signal ASICs. With in-house capabilities in packaging, test, failure analysis and reliability, Sandia offers a total supply-chain solution for high-reliability custom microelectronics for expanding national security applications.

Eiger Digital Rad-Hard ViArray

Digital Functions

• 276K Gates
• 368Kb Dual-Port SRAM
• 384Kb Configurable ROM
• 4 Oscillators
• 4 Phase Lock Loops
• 4 Power Supply Monitors
• 4 Power Partitions
• Isolated Unused Circuits
• 239 Configurable I/Os
• (PCI compatible)
• 8 Pairs LVDS I/Os

Whistler Mixed-Signal Rad-Hard ViArray

Analog Functions

• 2 Oscillators
• 2 Phase Locked Loops
• 4 Power Supply Monitors
• 4 Bandgap References
• 2 Chopper Bandgap/Bias
• 5 High Side Current Monitors
• 4 Low-Speed A-D Converters
• 4 Pipeline A-D Converters
• 8 D-A Converters, 8-bit
• 8 Multiplexers, 32:1
• 2 Temperature Sensors
• 64 Comparators
• 48 Amplifiers
• 128 Analog Switches
• 1 Analog Transient Recorder

Digital Functions

• 138K Gates
• 184Kb Dual-Port SRAM
• 192Kb Configurable ROM
• 4 Power Partitions
• Isolated Unused Circuits
• 239 Configurable I/Os (PCI compatible)
• 4 with High/Low Voltage Analog Inputs
• 8 Pairs LVDS I/Os

Technology

• 3.3 v
• 0.35 µm
• SOI CMOS

Package options

• 400 pin plastic BGA 27×27 mm
• Other package options in development

The Sandia Ultra-planar, Multi-level MEMS Technology 5 (SUMMiT VTM) Fabrication Process is a five-layer polycrystalline silicon surface micromachining process (one ground plane/electrical interconnect layer and four mechanical layers).

Motivation

While the devices made possible by fabrication using the four-layer SUMMiTTM Process are truly complex, there is further benefit in providing yet another layer of mechanical polysilicon. For example, with the SUMMiT VTM Process, more advanced systems can be created on moveable platforms (Figure 1). Much taller devices can be made (up to 12 microns high), making possible greater stiffness and mechanical robustness in the devices (Figure 2). The additional height can also be used to increase the force produced by actuators (Figure 3). The design flexibility in a five-layer technology is truly enormous – devices for applications that have not yet been imagined are now a possibility.

Fabrication

As with the SUMMiTTM Process, the SUMMiT VTM Fabrication Process is a batch fabrication process using conventional IC processing tools. Using this technology, high volume, low-cost production can be achieved. The processing challenges, including topography and film stress, are overcome using methods similar to those used in the SUMMiTTM Process: topography issues are mitigated by using Chemical-Mechanical Polishing (CMP) to achieve planarization, and stress is maintained at low levels using a proprietary process.

MEMS are also produced in the SUMMiT VTM Fabrication Process by alternately depositing a film, photolithographically patterning the film, and then performing chemical etching. By repeating this process with layers of silicon dioxide and polycrystalline silicon, extremely complex, inter-connected three-dimensional shapes can be formed. The photolithographic patterning is achieved with a series of two-dimensional "masks" that define the patterns to be etched. The SUMMiT VTM process uses 14 individual masks in the process, approximately the same quantity as in many CMOS IC processes.

Testimonials…

In relation to the SUMMiT V fabrication of a dual backplate capacitive MEMS Microphones, Dr. Toshi Nishida of the University of Florida said "We have developed a MEMS microphone using Sandia’s Ultra-planar, Multi-level, MEMS Technology (SUMMiT V) fabrication process. The microphone is a dual backplate capacitive microphone that may be operated in either open loop or closed loop mode. electrostatic force feedback. The microphone consists of a diaphragm and two porous backplates, one on either side of the diaphragm. The SUMMiT V fabrication process is unique in that it can meet the fabrication requirements of this project. All five layers of polysilicon are used in the fabrication of this device; Poly 0 is used for electrical connections, Poly 1 and Poly 2 are combined to form the lower backplate, Poly 3 is used for the diaphragm, and Poly 4 is used for the top backplate. The SUMMiT V process provides compliant mechanical layers that are ideal for the construction of the microphone’s diaphragm, especially due its use of chemical mechanical polishing to provide extremely flat structural layers and uniform spacing between the layers. The microphone demonstrates a flat frequency response, a linear response up to the designed limit, and a sensitivity which is close to the designed value. Sandia National Labs has been an essential partner in this project by providing access to and training for the SUMMiT V process."

Fairchild Semiconductor has said, The Summit™ technology is well recognized as the leading micromachining process for MEMS devices. "Network Photonics has worked with Sandia’s Summit IV™ technology and found the process to be a stable, well-characterized, platform for producing MEMS-based optical switching solutions," said Andy Goldstein, vice president of engineering for Network Photonics. "This process meets the high levels of reliability and performance Network Photonics requires for its customers." Fairchild is already in volume production of MEMS devices at its 6 inch wafer facility in South Portland. "We are pleased to see a company of Fairchild’s stature become a provider of our Summit IV™ technology," said Jay Jakubczak, Sandia deputy director for Defense Programs Microsystems Application. "It has been a goal of our MEMS effort to make our technology available for broad commercial applications and the relationship with Fairchild is an important step in achieving that goal.

Sandia has been providing access to the Summit™ Technology through its SAMPLES | Prototyping program that supports small quantities of MEMS devices. Making the Summit™ processing technology available through Fairchild significantly increases the volume of MEMS devices that can be manufactured.

Sandia SUMMiT™ V MEMS Devices launched aboard NASA ST5 Micro-Sats

A constellation of 3 Micro-satellites were ejected at 3 minute intervals during a launch aboard a Pegasus XL rocket on 22 March, 2006. The spacecrafts’ orbit is a "string of pearls," in a near-Earth polar elliptical orbit that will take them from approximately 300 kilometers (190 miles) to 4,500 kilometers (2,800 miles) from the Earth.

This was part of NASA’s Space Technology 5 (ST5) mission to explore concepts of building and operating miniaturized micro-sats. ST5 is the first step in developing missions of tens or hundreds of small spacecraft that would look at phenomena such as space weather.

The ST5 micro-sats will explore the Earth’s magnetic field using highly sensitive magnetometers, in addition to evaluating 10 technologies applicable to the development of micro-sats. One of the technologies being evaluated is Variable Emittance techniques for satellite thermal control which operates by either absorbing or reflecting heat. Two of the three satellites each contain 90 sq. cm of MEMS variable emittance louvers which were designed and fabricated at Sandia using the SUMMiT V™ (Sandia Ultra-planar, Multi-level MEMS Technology 5) MEMS fabrication technology. Sandia delivered the SUMMiT™ wafers to the Applied Physics Lab in fall 2001 for further processing and system integration as part of the joint development program with Johns Hopkins University Applied Physics Laboratory and NASA Goddard Spaceflight Center . The thermal performance of the variable emittance louvers will be evaluated during the 3 month mission.

"This is the first time a fully space-qualified device of this type has ever been flown, and the first to be flown on the outside of a satellite," says Ann Darrin, APL’s Vari-E program manager, who explained that the devices underwent the same rigorous tests that all space products undergo prior to launch. "It’s also the first demonstration of MEMS technology used to actively control temperature."

More information

John Hopkins Applied Physics Laboratory
Space Flight Now

In the last decade, devices manufactured with the SUMMiT ™ technology have demonstrated the capabilities of polysilicon surface micromachining. Currently Sandia is working on enhancements to this technology that utilize additional structural layers of silicon nitride to enable Microfluidics and BioMEMS applications. The addition of the silicon nitride layers allows the fabrication of microfluidic flow channels that are optically accessible (allowing observation) and insulating (allowing the placement of polysilicon electrodes at arbitrary locations in the flow channels). The goal of this effort is to provide functionality that is not feasible with other microfabrication technologies. The enhancements build on the key features of surface micromachining: manufacturability and compatibility with CMOS processing, which allow us to leverage the investment already made in microelectronics processing technology. Examples of devices fabricated using this technology include pumps, valves, and a cell manipulator.

Figure 4. Red blood cells flowing through the cellular manipulation device

Sandia designs, characterizes and delivers miniaturized, reliable RF MEMS components and systems such as filters, switches, and oscillators that provide differentiating capabilities to Sandia system groups impacting national security and nuclear weapons.

For more on RF MEMS see the MicroElectroMechanical Systems (MEMS) page.

Aluminum Nitride RF MEMS Resonators

Sandia has developed an aluminum nitride (AlN) process for fabricating RF MEMS micro resonators at frequencies ranging from 1 MHz to 3 GHz. This process uses the same equipment and materials that were developed to fabricate FBARS (film bulk acoustic resonators), which are widely used to implement cellular phone duplexers and filters at 1.9 GHz. Like FBARS, the piezoelectric transduction mechanism of these resonators allows the realization of low insertion loss filters. Unlike FBARS, Sandia’s AlN process allows resonators at any frequency between 1 MHz and 3 GHz to be fabricated on the same wafer because the resonant frequency is determined lithographically. The AlN resonator process also includes Sandia’s unique molded tungsten (W) capabilities. Incorporation of W into the AlN process eliminates the need for resonators that are suspended above the substrate by quarter-wave beams. It is this technology that allows the scaling of AlN resonators into the GHz range without introducing spurious modes, reductions in quality factor (Q), and with acceptable power handling for both the transmit and receive paths in full-duplex radios. This technology is most suited for realizing resonators from 1 MHz to 3 GHz, with Q’s approaching 5000, and impedances less than 300 Ohms.

Narrow-gap Polysilicon RF MEMS Resonators

A polysilicon MEMS resonator process has been developed at Sandia for the fabrication of high-Q oscillator references and intermediate frequency (IF) filters. This process can achieve electrode-to-resonator gaps less than 100 nm, which is needed to reduce the impedance of capacitively transduced devices. While high frequency resonators can be implemented in this process, it is best suited for fabricating resonators below 200 MHz because the impedance levels are significantly lower at these frequencies. Advantages of these polysilicon resonators when compared to microfabricated piezoelectric resonators include much higher Q (> 60,000), low drift, tunability, and low vibration sensitivity. These properties make polysilicon µresonators ideal for implementing miniature oscillators and IF filter banks for RF MEMS applications.

RF MEMS Reliability

Through measurement, characterization and analysis, we provide customer feedback to improve operation, performance and reliability of MEMS components, specifically RF switches. We have testing capabilities at the DARPA standard for MEMS switches (RFMIP) of 10 GHz. We have conducted environmentally controlled studies of switch performance and lifetimes at temperatures ranging from -15C to 75C, including cycling. Through failure analysis, we have worked with our customers to enhance understanding of operation, mechanically and electrically. We have performed tests to understand contamination issues that have caused early failures. We are investigating functionality and performance of RF sensor applications to monitor corrosion and to predict critical component failures. By utilizing knowledge of MEMS and by providing unique measurement and characterization capabilities, we can be an integral part of any MEMS project.

Sandia develops High-performance passive waveguide technologies for sensing and communication applications critical to our nation. Several planar lightwave circuit (PLC) technologies have been developed at Sandia that are ideally suited to applications where low-loss waveguides, thermo-optic switches, and high-Q resonators are needed.

Sandia’s strengths in modeling, design, fabrication, and testing have successfully produced ultra low loss, planar lightwave circuit (PLC) technologies with record low loss and high manufacturability in a fully operational CMOS fabrication line.

Figure 9. Lateral mode interference (LMI) 3 dB splitter: simulation (top left) and fabricated device (top rit), measured results (bottom)

Our Low Loss Silicon Nitride waveguide technology consists of a patterned Silicon Nitride optical waveguide core sandwiched between silicon dioxide cladding materials fabricated on a standard 6-inch silicon wafer. Process development efforts have demonstrated a polarization maintaining, single mode, optical waveguide, with record low attenuation of 0.1 dB/cm.

The index of refraction difference between the silicon nitride core material and the silicon dioxide cladding (2.01 vs. 1.45) makes this an ideal material system for designing small radius bends and complicated device geometries. Polysilicon heaters, metallized bondpads and mode expanding taper interfaces have been monolithically integrated and delivered with this principal PLC technology, and future micro-system integration efforts are under way for multi-material, multiple technology integration. For applications, such as resonant ring gyros where lower attenuation losses are desirable, accelerated process development is currently being executed to produce a (SiON/SiO2) technology with an attenuation goal of 0.05dB/cm or less.

Evanescent Wave Microring Biochemical Sensor

The transmission of a waveguide coupled high-Q microring resonator is sensitive to the perturbation of its optical path. A slight change of either the mode index or the microring physical size can cause a significant change in the transmission near its resonances. The high-Q integrated microring resonators can be used as ultra sensitive photonic transducers for a variety of sensor applications such as biochemical, gravity, acceleration, pressure, and electromagnetic sensing.

Microring biochemical sensor with a reference microring resonator

Fabricated Microring

Ring resonance for water

Ring resonance for methanol

Based on the evanescent wave and the high-Q microring resonator, Sandia demonstrated a liquid phase chemical sensor that can sense the small change of index of refraction of liquid phase chemicals. The on-chip evanescent wave microring biochemical sensors have the intrinsic capability and potential for large array multi-channel device integration and low cost mass production. Two parallel rings are used in transmission with separate input and output waveguides. One ring is the sense ring while the other is a reference ring embedded in a thick cladding and is not exposed to any biochemical liquids. On the top of the sense ring a window is etched to thin the cladding layer so that the evanescent wave can penetrate through it to reach the liquid. The input light is first coupled into the input waveguide and then split equally into two waveguides which are coupled to the reference ring and the sense ring. Two additional waveguides are used to couple the light out from the reference ring and the sense ring. A beam combiner is used to combine the light from the rings. As the input wavelength is scanned, we expect to see two distinct transmission resonances, one for each ring. The difference between these resonance frequencies is a direct measure of the refractive index of the liquid in the sense region.

Sandia has developed multiple passive waveguide technologies in combinations of the following materials:

• Silicon Dioxide
• Doped Silicon Dioxide
• Silicon Nitride
• Silicon Oxynitride
• Silicon on Insulator
• Polysilicon

The oxide molded tungsten process can be used for the fabrication of complex multilevel structures which can be relatively thick. The steps in the process are the deposition of a sacrificial oxide, patterning etching of the oxide, filling of the resulting mold by a blanket film of tungsten using chemical vapor deposition, and then removal of excess tungsten and planarization through chemical mechanical polishing. We have termed this process MOLTUN™ which is short for Molded Tungsten. This process has been used to demonstrate complex multilevel devices such as micro-mass-analysis systems up to 25 microns thick and novel latching relays which take advantage of the inherent tensile stress of the tungsten. Benefits of this process include high Z stiffness, high force actuation, high capacitance, maintenance of planarity and reduction or compensation for stress. Possible applications for MolTun™ include actuators, miniature mass analyzer, adaptive optics, and inertial sensors. Using current microfabrication process and materials it is possible to fabricate a wide very large variety of useful devices.

Micro-Mass-Analysis Systems Applications

MolTun™ has been used in Micro-Mass-Analysis Systems resulting in large (up to 106) arrays of cylindrical ion traps consisting of 4 separate electrode layers each separated by gaps. The devices are thicker than those achievable using traditional surface micro-machining and are far more complex than those achievable using deep trench etching. The pictures below show the highly complex W parts. The thickest parts fabricated for this project had ~14 layers of tungsten, 8 of which went into the fabrication of the ring electrode. The total thickness of the structures was ~25 microns. This is considerably thicker than typical polysilicon micromachined structures.

SEM micrographs of partially completed micro-mass-analysis systems.

Micro-Latching Relays

MolTun™ has also been used in micro-latching relays in which the design takes advantage of the internal tensile stress of the released W. The micro-mass analysis system is mechanically a static device and the residual tensile stress of the W is dealt with by simply anchoring the array firmly to the substrate. In the micro-latching relay this tensile stress is critical to the functioning of this mechanical device. The general design is based on having two pairs of opposing thermal actuators. The first picture below shows a typical released chevron type thermal actuator fabricated in the MOLTUN™ process. Initially the arms of the thermal actuator were at 4 degrees to the line between the pad centers. Upon release, the residual tensile stress of the W has pulled the arms of the thermal actuator straight. Our results show that the displacement can be considerable, tens of microns depending on geometry, and that angles greater than 4 degrees would be required to completely "relax" the tensile stress associated with these released W devices. In our latching relay design we place two orthogonal pairs of identical thermal actuators in opposition to each other, as seen in the second picture below. Since the system is symmetrical the overall displacement of the central shuttle is zero at rest. Passing a current to heat one of the heater arms causes it to expand and allows the opposing thermal actuator to reduce its internal stress by pulling the central shuttle towards it. The forces exerted in this design are always "pulling" in nature. In a conventional thermal actuator design the force generated is typically "pushing" in nature and when the force becomes sufficiently large the thermal actuator buckles and it becomes impossible to increase the actuation force. In our "pulling" W design it is impossible for the system to relax the force exerted by deforming into a buckling mode.

Top view optical micrograph of a released chevron thermal actuator fabricated using the MOLTUN™ process. Initially the arms of the thermal actuator were at 4 degrees to the line between the center of the two anchor pads. The residual stress in the W resulting from the thermal expansion mismatch between the Si and the W is sufficient to pull the arms straight.

Oblique angle SEM micrograph showing the latching relay design developed for the MOLTUN™ process. In this design two pairs of identical thermal actuators are arranged opposing each other and attached to each other through a suspension and a suspended plate. Since the system is symmetrical the overall displacement of the central shuttle is zero. Actuating one of the chevron thermal actuators allows the opposing thermal actuator to relax and pull back. Having two sets of orthogonal pairs of actuators enables X-Y translation of the central shuttle.

The opposing thermal actuation mechanism translates the top portion of the shuttle so that the two teeth engage. Once the teeth are engaged the actuation mechanism can be powered down and the structure remains latched in position. Two such structures electrically connect two pads through the moving shuttle.

MEMS devices are created with processing tools and infrastructure very similar to that used to fabricate conventional integrated circuits. Our advanced MEMS and integrated MEMS (IMEMS) are created in the Silicon Fab (SiFab), part of the Microsystems Engineering Sciences and Applications (MESA) Complex, located at Sandia National Laboratories. The SiFab is a world-class fabrication facility dedicated to providing development and engineering capabilities to support industry, government, and other programs of national interest.

Microsystems Engineering Sciences and Applications (MESA) Complex

Sandia National Laboratories (SNL) has invested heavily in the Microsystems and Engineering Sciences Applications (MESA) facility located in the heart of a multi-laboratory complex. Trusted custom fabrication of silicon and radiation-hardened process technologies for digital, analog and mixed signal ICs is currently available through MESA, which delivers production micro-electronics components to support special DOE and DOD programs. The MESA Complex is designed to integrate the numerous scientific disciplines necessary to produce functional, robust, integrated microsystems and represents the center of SNL’s investment in microsystems research, development, and prototyping activities. This suite of facilities encompasses approximately 400,000 square feet and includes cleanroom facilities, laboratories and offices.