Thermal-stress effects are shown to have a significant impact on the enhanced low-dose-rate sensitivity of linear bipolar circuits. Implications of these results on hardness assurance testing and mechanisms are discussed.
This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.
Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.
Scanning capacitance microscopy (SCM) was used to study the cross section of an operating p-channel MOSFET. We discuss the novel test structure design and the modifications to the SCM hardware that enabled us to perform SCM while applying dc bias voltages to operate the device. The results are compared with device simulations performed with DAVINCI.
Previous work showed the possible existence of a total-dose latch effect in fully-depleted SOI transistors that could severely limit the radiation hardness of SOI devices. Other work showed that worst-case bias configuration during irradiation was the transmission gate bias configuration. In this work we further explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10-keV x rays. Our results show no evidence for a total-dose latch effect as proposed by others. Instead, in absence of parasitic trench sidewall leakage, our data suggests that the increase in radiation-induced leakage current is caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current is amplified to considerably higher levels by impact ionization. Because the back-channel interface is in weak inversion, the top-gate bias can modulate the back-channel interface and turn the leakage current off at large, negative voltage levels. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. However, it is likely that this current also is amplified by impact ionization. For these transistors, the worst-case bias configuration was determined to be the ''ON'' bias configuration. These results have important implication on hardness assurance.
IEEE Transactions on Nuclear Science
Challenges related to radiation hardening CMOS technologies with shallow-trench isolation are explored. It is shown that developing a radiation-hardened CMOS technology with shallow trench isolation is more complex than using a traditional hardened field oxide as the trench insulator. We illustrate the use of device simulations in concert with measurements on test structures to provide detailed physical insight into methods for improving total-dose radiation response. Mechanisms that can limit the total-dose radiation hardness of shallow trench isolation such as high electric fields and ion implantation damage are explored. We demonstrate the successful conversion of a non-radiation hardened technology with LOCOS isolation (Sandia's CMOS6) into a greater than 1 Mrad(SiO2) radiation-hardened shallow-trench isolated technology (Sandia's CMOS6r). © 1998 IEEE.
Burn-in effects are used to demonstrate the potential impact of thermally activated aging effects on functional and parametric radiation hardness. These results have implications on hardness assurance testing. Techniques for characterizing aging effects are proposed.
Effects of irradiation and annealing temperature on radiation-induced charge densities are explored for MOS transistors. Both interface- and border-trap density increase with increasing radiation temperature, while the net oxide-trap charge density decreases.
The ionizing radiation response of several semiconductor process technologies has been shown to be enhanced by plastic packaging and/or pre-conditioning (burn-in). Potential mechanisms for this effect are discussed and data on bipolar linear circuits are presented.
Over the past 10 years, there have been a number of advances in methods to assess and assure the radiation hardness of microelectronics in military and space applications. At the forefront of these is the Qualified Manufacturers List (QML) methodology, in which the hardness of product is ``built-in`` through statistical process control (SPC) of technology parameters relevant to the radiation response, test structure to integrated circuit (IC) correlations, and techniques for extrapolating laboratory test results to varying radiation scenarios. At the same time, there has been renewed interest in the use of commercial technology -- with its enhanced performance, reduced cost, and higher reliability -- in military and space systems. In this paper, we initially demonstrate the application of QML techniques to assure and control the radiation response of hardened technologies. Through several examples, we demonstrate intra-die, wafer-to-wafer, and lot-to-lot variations in a hardened technology. We observe 10 to 30% variations in key technology parameters that result from variability in geometry, process, and design layout. Radiation-induced degradation is seen to mirror preirradiation characteristics. We then evaluate commercial technologies and report considerably higher variability in radiation hardness, i.e., variations by a factor of two to five. This variability is shown to arise from a lack of control of technology parameters relevant to the radiation response, which a commercial manufacturer has no interest in controlling in a normal process flow.
Significantly different radiation responses have been observed for both transistors and ICs with and without preirradiation burn-in. The hardness assurance implications of these results and possible changes to the MIL-STDs will be presented.
MOS total-dose response is shown to depend strongly on transistor gate length. Simple scaling models cannot predict short-channel device response from long-channel results. Hardness assurance implications are discussed for weapon and space environments.
The time dependence of radiation-induced interface-trap charge buildup for MOS transistors of varying gate-oxide thickness was investigated in order to clarify how the location of hydrogen in the SiO{sub 2} contributes to N{sub it} buildup. Radiation-induced interface-trap buildup in wet and dry gate oxides is compared for irradiations and anneals at constant positive bias and for negative-bias irradiations followed by positive-bias anneals. Implications of these results for different models of interface-trap buildup are discussed. 2 figs, 9 refs. (DLC)
A wafer-level test system, capable of 50-MHz data rates, is shown to support (1) process improvement and control and (2) test-structure-to-IC correlation efforts for total-dose hardness assurance. 11 refs., 3 figs.
The electric field dependence of radiation-induced interface-trap formation has been reported to be different for metal-gate capacitors and polysilicon-gate capacitors and transistors. For metal-gate capacitors, interface-trap formation steadily increases with increasing positive field. On the other hand, for polysilicon-gate capacitors and transistors, interface-trap buildup peaks near fields of 1 MV/cm to 2 MV/cm and decreases with an approximate E{sup {minus}1/2} dependence at higher fields. The previously reported field dependence for interface-trap generation for Al-gate capacitors is consistent at all fields with McLean's physical explanation of the two-stage process, which depends on hydrogen ion (H {sup +}) release in the bulk of the oxide as radiation-induced holes transport to either interface via polaron hopping. Above 1 MV/cm, the field dependence of interface-trap buildup for polysilicon-gate devices is inconsistent with this model. Instead, it is similar to the field dependence for hole-trapping in SiO{sub 2}, suggesting that hole trapping may play a key role in interface-trap generation in Si-gate devices. However, recent studies of the time-dependence of interface-trap buildup have known that hole trapping cannot be the rate-limiting step in interface-trap buildup in polysilicon gate devices. Consistent with McLean's physical explanation of the two-stage process, the rate-limiting step in interface-trap formation appears to be H{sup +} transport to the Si/SiO{sub 2} interface. We will show that the electric field dependence of radiation-induced oxide- and interface-trap charge buildup for both polysilicon and metal-gate transistors follows an approximate E{sup {minus}1/2} field dependence over a wide range of electric fields when electron-hole recombination effects are included. Based on these results a hole trapping/hydrogen transport (HT){sup 2} model for interface-trap buildup is proposed.