Publications

Marinella, M., Bennett, C., Jacobs-Gedrim, R.B., Hsia, A.W., Hughart, D.R., James, C.D., Vizkelethy, G., Bielejec, E.S., Agarwal, S., Fuller, E.J., Talin, A.A., Taggart, J., Barnaby, H., & Barnaby, H. (2019). Energy Efficient Neuromorphic Algorithm Training with Analog Memory Arrays [Conference Poster]. https://www.osti.gov/biblio/1641235

Marinella, M., Agarwal, S., Jacobs-Gedrim, R.B., Hughart, D.R., Bennett, C., Hsia, A.W., Fuller, E.J., Talin, A.A., Barnaby, H., & Barnaby, H. (2019). Efficient Neuromorphic Computing in SWaP-Constrained Environments [Conference Poster]. https://www.osti.gov/biblio/1641234

Marinella, M., Jacobs-Gedrim, R.B., Hsia, A.W., Hughart, D.R., James, C.D., Agarwal, S., Bortz-Johnson, A.J., Fuller, E.J., Talin, A.A., Barnaby, H., & Barnaby, H. (2019). Energy Efficient Neuromorphic Algorithm Training with Analog Memory Arrays [Conference Poster]. https://www.osti.gov/biblio/1641233

Marinella, M., Agarwal, S., Jacobs-Gedrim, R.B., Niroula, J., Goeke, R.S., Hsia, A.W., Fuller, E.J., Talin, A.A., James, C.D., & James, C.D. (2019). Toward an Analog Neural Accelerator with 10 fJ per Operation using Resistive Synaptic Devices [Conference Poster]. https://www.osti.gov/biblio/1641231

Marinella, M., Agarwal, S., Jacobs-Gedrim, R.B., Hsia, A.W., Hughart, D.R., Richter, I., Fuller, E.J., Plimpton, S.J., Talin, A.A., James, C.D., & James, C.D. (2019). Ultra-Efficient Neural Algorithm Accelerator Using Processing With Memory [Conference Poster]. https://www.osti.gov/biblio/1641230

Marinella, M., Agarwal, S., Jacobs-Gedrim, R.B., Hsia, A.W., Hughart, D.R., Richter, I., Fuller, E.J., Plimpton, S.J., Talin, A.A., James, C.D., & James, C.D. (2019). Ultra-Efficient Neural Algorithm Accelerator Using Processing With Memory (Poster) [Conference Poster]. https://www.osti.gov/biblio/1641229

Marinella, M., Agarwal, S., Jacobs-Gedrim, R.B., Hughart, D.R., Richter, I., Hsia, A.W., Fuller, E.J., Talin, A.A., Goeke, R.S., Plimpton, S.J., James, C.D., & James, C.D. (2019). Ultra-Efficient Neuromorphic Algorithm Acceleration Enabled by Resistive Memory (ReRAM) Crossbars [Conference Poster]. https://www.osti.gov/biblio/1641228

Marinella, M., Agarwal, S., Jacobs-Gedrim, R.B., Hughart, D.R., Richter, I., Hsia, A.W., Fuller, E.J., Talin, A.A., Goeke, R.S., Plimpton, S.J., James, C.D., & James, C.D. (2019). Ultra-Efficient Neuromorphic Algorithm Acceleration Enabled by Resistive Memory (ReRAM) Crossbars [Conference Poster]. https://www.osti.gov/biblio/1641227

Agarwal, S., Jacobs-Gedrim, R.B., Bennett, C., Hsia, A.W., Adee, S.M., Hughart, D.R., Fuller, E.J., Li, Y., Talin, A.A., Marinella, M., & Marinella, M. (2019). Designing and Modelling Analog Neural Network Training Accelerators [Conference Poster]. https://www.osti.gov/biblio/1640878

Agarwal, S., Jacobs-Gedrim, R.B., Bennett, C., Hsia, A.W., Adee, S.M., Hughart, D.R., Fuller, E.J., Li, Y., Talin, A.A., Marinella, M., & Marinella, M. (2019). Designing and Modelling Analog Neural Network Training Accelerators [Conference Poster]. https://www.osti.gov/biblio/1640877

Agarwal, S., Jacobs-Gedrim, R.B., Bennett, C., Hsia, A.W., van Heukelom, M., Hughart, D.R., Fuller, E.J., Li, Y., Talin, A.A., Marinella, M., & Marinella, M. (2019). Designing and modeling analog neural network training accelerators [Conference Poster]. 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. https://doi.org/10.1109/VLSI-TSA.2019.8804680

Marinella, M., Agarwal, S., Jacobs-Gedrim, R.B., Hughart, D.R., Richter, I., Hsia, A.W., Fuller, E.J., Talin, A.A., Goeke, R.S., Plimpton, S.J., James, C.D., & James, C.D. (2018). Energy Efficient Neuromorphic Algorithm Acceleration Enabled by Resistive Memory (ReRAM) Crossbars [Conference Poster]. https://www.osti.gov/biblio/1583083

Marinella, M., Agarwal, S., Jacobs-Gedrim, R.B., Hsia, A.W., Fuller, E.J., Talin, A.A., James, C.D., & James, C.D. (2018). Energy Efficient Neural Algorithm Training and Execution with Analog Crossbar Accelerators [Conference Poster]. https://www.osti.gov/biblio/1500185

Marinella, M., Niroula, J., Agarwal, S., Jacobs-Gedrim, R.B., Hughart, D.R., Hsia, A.W., James, C.D., & James, C.D. (2017). Piecewise empirical model (PEM) of resistive memory for pulsed analog and neuromorphic applications. Journal of Computational Electronics, 16(4), pp. 1144-1153. https://doi.org/10.1007/s10825-017-1107-3

Agarwal, S., Hsia, A.W., Jacobs-Gedrim, R.B., Hughart, D.R., Plimpton, S.J., James, C.D., Marinella, M., & Marinella, M. (2017). Designing an Analog Crossbar based Neuromorphic Accelerator [Conference Poster]. https://doi.org/10.1109/E3S.2017.8246155

Agarwal, S., Hsia, A.W., Jacobs-Gedrim, R.B., Hughart, D.R., Plimpton, S.J., James, C.D., Marinella, M., & Marinella, M. (2017). Designing an Analog Crossbar based Neuromorphic Accelerator [Conference Poster]. https://doi.org/10.1109/E3S.2017.8246155

Agarwal, S., Jacobs-Gedrim, R.B., Hsia, A.W., Hughart, D.R., Fuller, E.J., Talin, A.A., James, C.D., Plimpton, S.J., Marinella, M., & Marinella, M. (2017). Achieving ideal accuracies in analog neuromorphic computing using periodic carry [Conference Poster]. Digest of Technical Papers - Symposium on VLSI Technology. https://doi.org/10.23919/VLSIT.2017.7998164

Niroula, J., Agarwal, S., Jacobs-Gedrim, R.B., Hughart, D.R., Hsia, A.W., James, C.D., Marinella, M., & Marinella, M. (2017). Compact Model of Resistive Memory Devices for Pulsed Analog and Neuromorphic Applications [Presentation]. https://www.osti.gov/biblio/1508478

Agarwal, S., Jacobs-Gedrim, R.B., Hsia, A.W., Hughart, D.R., Fuller, E.J., Talin, A.A., James, C.D., Plimpton, S.J., Marinella, M., & Marinella, M. (2017). Achieving Ideal Accuracies in Analog Neuromorphic Computing Using Periodic Carry [Conference Poster]. https://doi.org/10.23919/VLSIT.2017.7998164

Agarwal, S., Plimpton, S.J., Hughart, D.R., Hsia, A.W., Richter, I., Cox, J.A., James, C.D., Marinella, M., & Marinella, M. (2016). Resistive memory device requirements for a neural algorithm accelerator [Conference Poster]. Proceedings of the International Joint Conference on Neural Networks. https://doi.org/10.1109/IJCNN.2016.7727298

Agarwal, S., Plimpton, S.J., Hughart, D.R., Hsia, A.W., Richter, I., Cox, J.A., James, C.D., Marinella, M., & Marinella, M. (2016). Resistive memory device requirements for a neural algorithm accelerator [Conference Poster]. Proceedings of the International Joint Conference on Neural Networks. https://doi.org/10.1109/IJCNN.2016.7727298

James, C.D., Severa, W., Draelos, T.J., Aimone, J.B., Vineyard, C.M., Agarwal, S., Hsia, A.W., Hughart, D.R., Finnegan, P.S., Jacobs-Gedrim, R.B., Fuller, E.J., Talin, A.A., Marinella, M., Schiek, R.L., Plimpton, S.J., & Plimpton, S.J. (2016). Neural machine learning algorithms and hardware for image analysis and data science applications [Conference Poster]. https://www.osti.gov/biblio/1398356

Marinella, M., Agarwal, S., Plimpton, S.J., Talin, A.A., el Gabaly Marquez, F., Fuller, E.J., Hughart, D.R., Parekh, O., Debenedictis, E., Goeke, R.S., Hsia, A.W., Aimone, J.B., James, C.D., & James, C.D. (2016). Emerging Technologies for the Acceleration of Neuromorphic Algorithms [Conference Poster]. https://www.osti.gov/biblio/1505271

Marinella, M., Agarwal, S., Talin, A.A., McCormick, F.B., Plimpton, S.J., el Gabaly Marquez, F., Fuller, E.J., Jacobs-Gedrim, R.B., Hughart, D.R., Goeke, R.S., Hsia, A.W., & Hsia, A.W. (2016). Device to System Modeling Framework to Enable a 10 fJ per Instruction Neuromorphic Computer [Conference Poster]. https://www.osti.gov/biblio/1372152

Marinella, M., Agarwal, S., Fuller, E.J., Talin, A.A., el Gabaly Marquez, F., Jacobs-Gedrim, R.B., Hughart, D.R., Goeke, R.S., Hsia, A.W., Schiek, R.L., Plimpton, S.J., James, C.D., & James, C.D. (2016). Neuromorphic Algorithm Acceleration with Resistive Memory NanoCrossbars [Presentation]. https://www.osti.gov/biblio/1373226