Publications

The inability to do visual solder joint inspection has been a major road block to using advanced ICs with high I/O count in area array packaging technologies like flip-chip, Quad Flat No Lead (QFN) and Ball grid Arrays (BGAs). In this paper, we report the results of a study to evaluate 3D X-Ray Computed Tomography (3DXRay-CT) as a solder inspection technique for area array package assemblies. We have conducted an experiment with board assemblies having intentionally designed solder defects like cold solder joints, solder-mask defects, unfilled vias in solder pads, and different shape and size solder pads. We have demonstrated that 3D X-Ray-CT technique was able to detect all these defects. This technique is a valid technique to inspect solder joints in area array packaging technologies.

We report a new wafer-level packaging technology for miniature MEMS in a hermetic micro-environment. The unique and new feature of this technology is that it only uses low cost wafer-level processes such as eutectic bonding, Bosch etching and mechanical lapping and thinning steps as compared to more expensive process steps that will be required in other alternative wafer-level technologies involving thru-silicon vias or membrane lids. We have demonstrated this technology by packaging silicon-based AlN microsensors in packages of size 1.3 1.3 mm2 and 200 micrometer thick. Our initial cost analysis has shown that when mass produced with high yields, this device will cost $0.10 to $0.90. The technology involves first preparing the lid and MEMS wafers separately with the sealring metal stack of Ti/Pt/Au on the MEMS wafers and Ti/Pt/Au/Ge/Au on the lid wafers. On the MEMS wafers, the Signal/Power/Ground interconnections to the wire-bond pads are isolated from the sealring metallization by an insulating AlN layer. Prior to bonding, the lid wafers were Bosch-etched in the wirebond pad area by 120 um and in the center hermetic device cavity area by 20 um. The MEMS and the lid wafers were then aligned and bonded in vacuum or in a nitrogen environment at or above the Au-Ge Eutectic temperature, 363C. The bonded wafers were then thinned and polished first on the MEMS side and then on the lid side. The MEMS side was thinned to 100 ums with a nearly scratch-free and crack-free surface. The lid side was similarly thinned to 100 ums exposing the wire-bond pads. After thinning, a 100 um thick lid remained over the MEMS features providing a 20 um high hermetic micro-environment. Thinned MEMS/Lid wafer-level assemblies were then sawed into individual devices. These devices can be integrated into the next-level assembly either by wire-bonding or by surface mounting. The wafer-level packaging approach developed in this project demonstrated RF Feedthroughs with 0.3 dB insertion loss and adequate RF performance through 2 GHz. Pressure monitoring Pirani structures built inside the hermetic lids have demonstrated the ability to detect leaks in the package. In our preliminary development experiments, we have demonstrated 50% hermetic yields. © 2011 IEEE.

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The next generation of integrated micro-system technologies can only keep up with increased functionality and performance demands by using the 3rd dimension. The primary drivers for 3D integration are miniaturization, integration of different technologies in a small form-factor, and performance. 3D integration technologies can be grouped into 3 main categories, namely 3D On-chip integration, 3D IC-stacking, and 3D-packaging. This chapter provides a detailed review of each of these categories. © 2009 Springer-Verlag US.

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A critical issue in the long-term reliability of solder connections used in electronic packages is joint failure during thermal cycling. At present, solder is assumed to be a homogeneous single-phase metal in most finite element analyses to predict solder joint fatigue failures. However, in the last decade, several metallurgical studies have shown that solder microstructure may have a role in early solder joint failures. Investigators have observed that solder microstructure coarsens in local bands during aging and during thermal cycle fatigue. In a failed solder joint, the fatigue cracks are found in these bands of coarse grains. It is speculated that the grain coarsening increases local strains within the microstructure, thereby increasing the likelihood for a crack to initiate. The objective of this study is to model and simulate the effect of grain coarsening on local stresses and strains. During solidification of eutectic Pb/Sn solder, two types of microstructures form: lamellar and equiaxed. In this study, the author has developed a computer code to generate both types of microstructures of varying grain coarseness. This code is incorporated into the finite element code that analyzes the local stresses and strains within the computer-generated microstructure. The FE code, specifically developed for this study, uses an algorithm involving the sparse matrix and iterative solver. This code on a typical single-processor machine will allow the analyst to use over 1 million degrees of freedom.

Sandia National Laboratories has developed a chip scale packaging technology called mini Ball Grid Array (mBGA). The mBGA is a flip chip die, obtained by redistributing peripheral pads in existing dies to an area array of pads 10 mils or larger in diameter with a minimum pitch of 20 mils. The peripheral pads are redistributed to area array pads using two polyimide dielectric and two metal conductor layers. mBGA can be closely tiled together on a substrate to yield a very high circuit density. In an earlier report, we presented the results on the reliability and thermal performance of mBGA on silicon and ceramic substrates. In this report, we present an mBGA cost analysis, improvement in the mBGA bump adhesion, and reliability and thermal performance of mBGA assemblies on FR-4 boards.

A new die-level packaging technology, mBGA, is reported in this paper. The mBGA enables high circuit packaging density on multichip module (MCM), facilitates die testing to obtain ``known good die,`` and allows a cost effective module assembly. We have designed and fabricated a test vehicle to evaluate mBGA multichip module technology. This paper describes the mBGA technology and the test vehicle multichip module and reports preliminary results on the die test and burn-in, thermal performance and reliability studies.

Ceramic chip capacitors can potentially crack due to thermal stresses in a surface mount assembly process. The electrical performance of the cracked capacitors will degrade with time, and they will prematurely short. In high reliability applications, the cracked capacitors must be identified and eliminated. We have developed and demonstrated the temperature-humidity-bias (THB) aging technique to identify cracked capacitors. The initial phase of the study involved setting up automated test equipment to monitor 100 surface mounted capacitors at 85% relative humidity, 85{degree}C with 50 volts dc bias. The capacitors subjected to severe thermal shock were aged along with control samples. Failure mode analysis was done on the failed capacitors. The capacitors with surface cracks short-out within the first 8 hours of aging, whereas the capacitors that failed after a longer aging time (8 to 1000 hours) had a shorting path in an internal void. Internal voids are typical defects introduced during manufacturing of multilayer ceramic (MLC) capacitors. In the second phase of the study, we used the THB aging technique to study the effect of surface mount processes on capacitor cracking and, thus the reliability. The surface mount processes studied were vapor phase, infra-red (IR) and convection belt reflow soldering. The results shoed that 6.3% of vapor phase soldered capacitors, and 1.25% of the IR and convection belt soldered capacitors had cracks. In all capacitors, regardless of the solder process used, an additional 3 to 4% of the capacitors failed due to a shorting path in the internal void. The results of this study confirm that this technique can be used to screen cracked capacitors and compare different solder and manufacturing processes.