Publications
Search results
Jump to search filtersAn AMR Task Dependency Analysis and Communications Simulation Methodology
A Synthetic Task Model for HPC-Grade Optical Network Performance Evaluation
The role of optical links in HPC system interconnects
2013 Optical Interconnects Conference, OI 2013
Presentation: Validating extreme-scale HPC simulation through Bayesian inference uncertainty quantification
SST/macro: A coarse-grained simulation workflow
Validating the Simulation of Large-scale Parallel Applications Using Statistical Characteristics
SST/macro: A Macroscale Event Simulator for Extreme-Scale Computing
Tutorial on Modeling Exascale Applications with SST/macro and Eiger
Execution Models for Exascale- A Bottom-Up Approach -(EMBU)
SST/macro primer
SST/macro: A Macroscale Event Simulator for Extreme-Scale Computing
Probabilistic Schwarz Coupling for Fault-Tolerance and Scalability
Automatic Extraction of Software Skeletons for Benchmarking Large-Scale Parallel Applications
Using VTK to Represent HPC Simulations with SST/macro
Validating extreme-scale HPC simulation through Bayesian inference uncertainty quantification
Decreasing network power with on-off links informed by scientific applications
Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013
A Deep Dive Analysis of Hardware Design Trade-offs for Exascale Combustion Applications
Programming Scientific Applications Now for the Integration of Silicon Photonics
The Role of Optical Links in HPC System Interconnects
Eiger :
Multi-Layer Silicon Nanophotonic Network Chips for High-Performance Computing
Proposed for publication in Journal of Parallel and Distributed Computing.
SST/macro: A Macroscale Event Simulator for Exascale Co-&%23173-design
Enabling Exascale Co-design with The Structural Simulation Toolkit
Multi-Layer Silicon Nanophotonic Network Chips for High-Performance Computing
Evaluation Optimization and Application of Execution Models for Exascale Computing
SST: A Simulator for Exascale Co-design
Coarse-Grain Simulation of Networks-on-Chip using SST/Macro
28 Results