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Samba: A Detailed Memory Management Unit (MMU) for the SST Simulation Framework

Awad, Amro; Voskuilen, Gwendolyn R.; Hammond, Simon; Hoekstra, Robert J.

The Memory Management Unit (MMU) is one of the most important parts of any modern computing system. It can be thought of as the hardware support for virtual memory, which enforces access permissions, and manages the translation of processes' virtual addresses into real memory physical addresses. The operating system (OS) allocates the physical memory in a small granularity frames that can be accessed by processes with appropriate permissions. Each process has the illusion of having an entire memory space, however, the actual addresses issued by the process, (`virtual addresses'), are translated into the physical frame address allocated by the OS through virtual memory.

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TYPE SAND Report YEAR 2016
DOIOSTI

Analyzing allocation behavior for multi-level memory

ACM International Conference Proceeding Series

Voskuilen, Gwendolyn R.; Rodrigues, Arun; Hammond, Simon

Managing multi-level memories will require different policies from those used for cache hierarchies, as memory technologies differ in latency, bandwidth, and volatility. To this end we analyze application data allocations and main memory accesses to determine whether an application-driven approach to managing a multi-level memory system comprising stacked and conventional DRAM is viable. Our early analysis shows that the approach is viable, but some applications may require dynamic allocations (i.e., migration) while others are amenable to static allocation.

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TYPE Conference Poster YEAR 2016
DOIOSTIScopus

Evaluating the Opportunities for Multi-Level Memory – An ASC 2016 L2 Milestone

Voskuilen, Gwendolyn R.; Rodrigues, Arun; Frank, Michael P.; Hammond, Simon

The next two Advanced Technology platforms for the ASC program will feature complex memory hierarchies – in the Trinity supercomputer being deployed in 2016, Intel’s Knights Landing processors will feature 16GB of on-package, high-bandwidth memory, combined with a larger capacity DDR4 memory and in 2018, the Sierra machine deployed at Lawrence Livermore National Laboratory will feature powerful compute nodes containing POWER9 processors with large capacity memories and an array of coherent GPU accelerators also with high bandwidth memories.

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TYPE SAND Report YEAR 2016
DOIOSTI
Results 151–175 of 272
Results 151–175 of 272