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Neuromorphic Graph Algorithms

Parekh, Ojas D.; Wang, Yipu W.; Ho, Yang H.; Phillips, Cynthia A.; Pinar, Ali P.; Aimone, James B.; Severa, William M.

Graph algorithms enable myriad large-scale applications including cybersecurity, social network analysis, resource allocation, and routing. The scalability of current graph algorithm implementations on conventional computing architectures are hampered by the demise of Moore’s law. We present a theoretical framework for designing and assessing the performance of graph algorithms executing in networks of spiking artificial neurons. Although spiking neural networks (SNNs) are capable of general-purpose computation, few algorithmic results with rigorous asymptotic performance analysis are known. SNNs are exceptionally well-motivated practically, as neuromorphic computing systems with 100 million spiking neurons are available, and systems with a billion neurons are anticipated in the next few years. Beyond massive parallelism and scalability, neuromorphic computing systems offer energy consumption orders of magnitude lower than conventional high-performance computing systems. We employ our framework to design and analyze new spiking algorithms for shortest path and dynamic programming problems. Our neuromorphic algorithms are message-passing algorithms relying critically on data movement for computation. For fair and rigorous comparison with conventional algorithms and architectures, which is challenging but paramount, we develop new models of data-movement in conventional computing architectures. This allows us to prove polynomial-factor advantages, even when we assume a SNN consisting of a simple grid-like network of neurons. To the best of our knowledge, this is one of the first examples of a rigorous asymptotic computational advantage for neuromorphic computing.

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Analysis and mitigation of parasitic resistance effects for analog in-memory neural network acceleration

Semiconductor Science and Technology

Xiao, Tianyao X.; Feinberg, Benjamin F.; Rohan, Jacob N.; Bennett, Christopher H.; Agarwal, Sapan A.; Marinella, Matthew J.

To support the increasing demands for efficient deep neural network processing, accelerators based on analog in-memory computation of matrix multiplication have recently gained significant attention for reducing the energy of neural network inference. However, analog processing within memory arrays must contend with the issue of parasitic voltage drops across the metal interconnects, which distort the results of the computation and limit the array size. This work analyzes how parasitic resistance affects the end-to-end inference accuracy of state-of-the-art convolutional neural networks, and comprehensively studies how various design decisions at the device, circuit, architecture, and algorithm levels affect the system's sensitivity to parasitic resistance effects. A set of guidelines are provided for how to design analog accelerator hardware that is intrinsically robust to parasitic resistance, without any explicit compensation or re-training of the network parameters.

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Credible, Automated Meshing of Images (CAMI)

Roberts, Scott A.; Donohoe, Brendan D.; Martinez, Carianne M.; Krygier, Michael K.; Hernandez-Sanchez, Bernadette A.; Foster, Collin W.; Collins, Lincoln; Greene, Benjamin G.; Noble, David R.; Norris, Chance A.; Potter, Kevin M.; Roberts, Christine C.; Neal, Kyle D.; Bernard, Sylvain R.; Schroeder, Benjamin B.; Trembacki, Bradley; Labonte, Tyler; Sharma, Krish; Ganter, Tyler G.; Jones, Jessica E.; Smith, Matthew D.

Abstract not provided.

Investigating Volumetric Inclusions of Semiconductor Materials to Improve Flashover Resistance in Dielectrics

Steiner, Adam M.; Siefert, Christopher S.; Shipley, Gabriel A.; Redline, Erica M.; Dickens, Sara D.; Jaramillo, Rex J.; Chavez, Tom C.; Hutsel, Brian T.; Laros, James H.; Peterson, Kyle J.; Bell, Kate S.; Balogun, Shuaib; Losego, Mark; Sammeth, Torin; Kern, Ian; Harjes, Cameron; Gilmore, Mark A.; Lehr, Jane

Abstract not provided.

Results 201–225 of 9,998
Results 201–225 of 9,998