Publications

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Abstract not provided.

Abstract not provided.

This work combines focused ion beam sputtering and ultra-precision machining as a first step in fabricating metal alloy microcomponents. Micro-end mills having ∼25 μm diameters are made by sputtering cobalt M42 high-speed steel and C2 micrograin tungsten carbide tool blanks. A 20 keV focused gallium ion beam is used to define a number of cutting edges and tool end clearance. Cutting edge radii of curvature are less than or equal to 0.1 μm. Micro-end mill tools having 2, 4 and 5 cutting edges successfully machine millimeter long trenches in 6061-T4 aluminum, brass, 4340 steel and polymethyl methacrylate. Machined trench widths are approximately equal to the tool diameters, and surface roughnesses (Ra) at the bottom of micromachined features are ∼200 nm. Microtools are robust and operate for more than 6 h without fracture. Results from ultra-precision machining aluminum alloy at feed rates as high as 50 mm/minute and an axial depth of 1.0 μm are included. © 2001 Elsevier Science Inc.

Commercial focused ion beam (FIB) systems are commonly used to image integrated circuits (ICS) after device processing, especially in failure analysis applications. FIB systems are also often employed to repair faults in metal lines for otherwise functioning ICS, and are being evaluated for applications in film deposition and nanofabrication. A problem that is often seen in FIB imaging and repair is that ICS can be damaged during the exposure process. This can result in degraded response or out-right circuit failure. Because FIB processes typically require the surface of an IC to be exposed to an intense beam of 30--50 keV Ga{sup +} ions, both charging and secondary radiation damage are potential concerns. In previous studies, both types of effects have been suggested as possible causes of device degradation, depending on the type of device examined and/or the bias conditions. Understanding the causes of this damage is important for ICS that are imaged or repaired by a FIB between manufacture and operation, since the performance and reliability of a given IC is otherwise at risk in subsequent system application. In this summary, the authors discuss the relative roles of radiation damage and charging effects during FIB imaging. Data from exposures of packaged parts under controlled bias indicate the possibility for secondary radiation damage during FIB exposure. On the other hand, FIB exposure of unbiased wafers (a more common application) typically results in damage caused by high-voltage stress or electrostatic discharge. Implications for FIB exposure and subsequent IC use are discussed.

This work combines focused ion beam sputtering and ultra-precision machining as a first step in fabricating microstructure in metals and alloys. Specifically, {approx}25{micro}m diameter micro-end mills are made from cobalt M42 high-speed steel and C2 micrograin tungsten carbide tool blanks by ion beam sputtering. A 20 keV focused gallium beam defines tool cutting edges having radii of curvature < 0.1{micro}m. Micro-end mills having 2, 4 and 5 cutting edges successfully machine small trenches in 6061-T4 aluminum, brass, 4340 steel and polymethyl methacrylate. Machined trench widths are approximately equal to the tool diameters and surface roughnesses (rms) are {approx}150 nm or less. Microtools are robust and operate for more than 6 hours without fracture. Results from ultra-precision machining aluminum at feed rates as high as 50 mm/minute are included.

We report on recent studies of the effects of 50 keV focused ion beam (FIB) exposure on MOS transistors. We demonstrate that the changes in value of transistor parameters (such as threshold voltage, V{sub t}) are essentially the same for exposure to a Ga+ ion beam at 30 and 50 keV under the same exposure conditions. We characterize the effects of FIB exposure on test transistors fabricated in both 0.5 {micro}m and 0.225 {micro}m technologies from two different vendors. We report on the effectiveness of overlying metal layers in screening MOS transistors from FIB-induced damage and examine the importance of ion dose rate and the physical dimensions of the exposed area.

Both the increased complexity of integrated circuits, resulting in six or more levels of integration, and the increasing use of flip-chip packaging have driven the development of integrated circuit (IC) failure analysis tools that can be applied to the backside of the chip. Among these new approaches are focused ion beam (FIB) tools and processes for performing chip edits/repairs from the die backside. This paper describes the use of backside FIB for a failure analysis application rather than for chip repair. Specifically, they used FIB technology to prepare an IC for inspection of voided metal interconnects (lines) and vias. Conventional FIB milling was combined with a super-enhanced gas assisted milling process that uses XeF{sub 2} for rapid removal of large volumes of bulk silicon. This combined approach allowed removal of the TiW underlayer from a large number of Ml lines simultaneously, enabling rapid localization and plan view imaging of voids in lines and vias with backscattered electron (BSE) imaging in a scanning electron microscopy (SEM). Sequential cross sections of individual voided vias enabled them to develop a 3-d reconstruction of these voids. This information clarified how the voids were formed, helping to identify the IC process steps that needed to be changed.

The electrical and chemical properties of insulators produced by codeposition of siloxane compounds or TEOS with oxygen in a focused ion beam (FIB) system were investigated. Metal-insulator-metal capacitor structures were fabricated and tested. Specifically, leakage current and breakdown voltage were measured and used to calculate the effective resistance and breakdown field. Capacitance measurements were performed on a subset of the structures. It was found that the siloxane-based FIB-insulators had superior electrical properties to those based on TEOS. Microbeam Rutherford backscattering spectrometry analysis and Fourier transform infrared spectroscopy were used to characterize the films and to help understand the differences in electrical behavior as a function of gas chemistry and deposition conditions. Finally, a comparison is made between the results presented here, previous results for FIB-deposited insulators, and typical thermally-grown gate oxides and interlevel dielectric SiO{sub 2} insulators.

We present two new techniques that enhance conventional focused ion beam (FIB) system capabilities for integrated circuit (IC) analysis: in situ electrical biasing and voltage contrast imaging. We have used in situ electrical biasing to enable a number of advanced failure analysis applications including (1) real time evaluation of device electrical behavior during milling and deposition, (2) verification of IC functional modifications without removal from the FIB system, and (3) ultraprecision control for cross sectioning of deep submicron structures, such as programmed amorphous silicon antifuses. We have also developed FIB system voltage contrast imaging that can be used for a variety of failure analysis applications. The use of passive voltage contrast imaging for defect localization and for navigation on planarized devices will be illustrated. In addition, we describe new, biased voltage contrast imaging techniques and provide examples of their application to the failure analysis of complex ICs. We discuss the necessary changes in system operating parameters to perform biased voltage contrast imaging.

This report describes the first practical, non-invasive technique for detecting and imaging currents internal to operating integrated circuits (ICs). This technique is based on magnetic force microscopy and was developed under Sandia National Laboratories` LDRD (Laboratory Directed Research and Development) program during FY 93 and FY 94. LDRD funds were also used to explore a related technique, charge force microscopy, for voltage probing of ICs. This report describes the technical work performed under this LDRD as well as the outcomes of the project in terms of publications and awards, intellectual property and licensing, synergistic work, potential future work, hiring of additional permanent staff, and benefits to DOE`s defense programs (DP).

This invited paper describes recently reported work on the application of magnetic force microscopy (MFM) to image currents in IC conductors [1]. A computer model for MFM imaging of IC currents and experimental results demonstrating the ability to determine current direction and magnitude with a resolution of {approximately} 1 mA dc and {approximately} 1 {mu}A ac are presented. The physics of MFM signal generation and applications to current imaging and measurement are described.

Magnetic force microscopy (MFM) has been applied to image currents in internal IC conductors. We present a model for the MFM imaging of IC currents, describe MFM signal generation, and demonstrate the ability to analyze current direction and magnitude with a sensitivity of {approximately} 1 mA dc and {approximately} 1 {mu}A ac. Our experimental results are a significant improvement on the 100 mA ac resolution previously reported using an electron beam to detect IC currents [1].

Analysis of an intermittent failure to write the 1'' state to a particular memory location at low temperature ({minus}55{degree}C) in a 16K {times} 1 CMOS SRAM is presented. The failure was found to be due to an open metallization at a metal-to-silicon contact. The root cause of the failure was poor step coverage of the metallization over an oxide step. A variety of failure analysis techniques including dynamic electron beam analysis at low temperature using a Peltier cold stage were employed to study the intermittently failing SRAM. The failure site was located by using capacitive coupling voltage contrast analysis. PSPICE simulation, light emission microscopy, scanning electron microscopy, and focused-ion beam techniques were used to confirm the failure mechanism and location. The write cycle time of the failed IC was abnormally long, but within the allowable tester limit. The vulnerability of other ICs to failure by open metallization in metal-to-silicon contacts is reviewed. 8 refs., 10 figs., 2 tabs.