Publications

Scan path testing and debugging offers a structured, proven way to debug and test arbitrarily complex electronic systems. The interface and equipment requirements are far lower than traditional debug and test techniques. The system is also completely testable even when physically remote from the lab where it was originally developed. This report describes our experience using scan techniques to debug the EPSILON-2 processor board, a system with over 300 ICs and over 2500 independently controllable and observable test points. The debug time of the circuit was greatly reduced by the adoption of scan path methodology. The use of expensive test equipment was drastically reduced, and the level of control of the circuitry increased. We have run tests on the processor from physically remote sites. Our experiences are described, and the adoption of scan path techniques is shown to be simple enough that it should be useful in all electronic projects. 8 refs., 12 figs.

EPSILON-2 is a general parallel computer architecture that combines the fine grain parallelism of dataflow computing with the sequential efficiency common to von Neumann computing. Instruction level synchronization, single cycle context switches, and RISC-like sequential efficiency are all supported in EPSILON-2. The general parallel computing model of EPSILON-2 is described, followed by a description of the processing element architecture. A sample code is presented in detail, and the progress of the physical implementation discussed. 11 refs., 14 figs.