Publications Details

The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process

Ahlbin, J.R.; Gadlage, M.J.; Ball, D.R.; Witulski, A.W.; Bhuva, B.L.; Reed, R.A.; Vizkelethy, G.; Massengill, L.W.

Heavy-ion microbeam and broadbeam data are presented for a 65 nm bulk CMOS process showing the existence of pulse quenching at normal and angular incidence for designs where the pMOS transistors are in common n-wells or isolated in separate n-wells. Experimental data and simulations show that pulse quenching is more prevalent in the common n-well design than the separate n-well design, leading to significantly reduced SET pulsewidths and SET cross-section in the common n-well design. © 2010 IEEE.