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2K nonvolatile shadow RAM and 256K EEPROM SONOS nonvolatile memory development

Biennial IEEE International Nonvolatile Memory Technology Conference

Nasby, R.D.S.

This paper describes SONOS nonvolatile memory development at Sandia National Laboratories. A 256K EEPROM nonvolatile memory and a 2K nonvolatile shadow RAM are under development using an n-channel SONOS memory technology. The technology has 1.2 μm minimum features in a twin well design using shallow trench isolation.

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Application of chemical-mechanical polishing to planarization of surface-micromachined devises

Nasby, R.D.S.

Chemical-Mechanical Polishing (CMP) has emerged as an enabling technology for manufacturing multi-level metal interconnects used in high-density Integrated Circuits (IC). In this work we present extension of CMP from sub-micron IC manufacturing to fabrication of complex surface-micromachined Micro-ElectroMechanical Systems (MEMS). This planarization technique alleviates processing problems associated with fabrication of multi-level polysilicon structures, eliminates design constraints linked with non-planar topography, and provides an avenue for integrating different process technologies. We discuss the CMP process and present examples of the use of CMP in fabricating MEMS devices such as microengines, pressures sensors, and proof masses for accelerometers along with its use for monolithically integrating MEMS devices with microelectronics.

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Properties and characterization of thin film ferroelectric capacitors for nonvolatile memories

Nasby, R.D.S.

Thin film ferroelectric materials are the basis for a new, promising IC nonvolatile memory technology. The primary material being studied for ferroelectric memories is PZT. One of the key factors in determining the feasibility of PZT ferroelectric memories for weapon or space applications is whether PZT ferroelectric technology can be integrated into a radiation-hardened CMOS or bipolar process. Sandia National Laboratories has a program to study ferroelectric/CMOS process integration issues. The primary goal of this program is to determine if radiation-hardened reliable ferroelectric/CMOS IC memories can be fabricated. This program includes both the fabrication and characterization of ferroelectric test capacitors. In this paper we will give a brief overview of the program, discuss techniques developed to characterize ferroelectric devices for retention and endurance, and give results on studies of fatigue and retention of capacitors.

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3 Results
3 Results