Portals 4.0, released in 2012, was developed as a result of the lessons learned from Portals 3.3 and the Cray XT platform. Even when attached via HyperTransport, the NIC proved sufficiently far from the host processor to motivate an API in which most operations do not require a round-trip to the NIC. In particular, Portals provides building blocks for implementing the unexpected message handling of MPI on the NIC, eliminating the need for blocking round-trips to update memory descriptor state. Portals 4.0 also adds a number of features to improve message rate for PGAS languages and libraries, as well as a facility for offloading collective operations.
Portals 3.3, released in 2003, was developed as part of the Cray/Sandia collaboration to build ASC Red Storm, the first of Cray’s highly successful XT line of supercomputers. Portals 3.3 introduced the ability to only transfer a subset of the memory descriptor, as well as a number of small cleanups from Portals 3.0.
Portals 3.0, released in 1998, was designed as part of the Cplant cluster platform developed at Sandia. Cplant utilized commodity Myrinet network intefaces (with a custom firmware) to implement the Portals messaging semantics. Portals 3.0 was the first version of Portals to provide a functional API, and was developed to account for the long latencies from network interface to host memory found in PCI-based network interfaces.
Portals 2.0, developed in 1994, added message selection with match lists and a number of different memory descriptor types. Messaging operations were still controlled by the manipulation of portals structures in user space. Portals 2.0 was used with the Puma/Cougar operating systems on the ASCI Red system, the first TeraFLOPS MPP.
Portals 1.0 was published in 1993, but never implemented. It provided data structures in user-space to control message delivery, as well as both kernel-managed and user-managed memory descriptors.
The first version of Portals was developed in 1991 as part of the SUNMOS (Sandia/UNM OS) project, running on the nCUBE and Intel Paragon. The platforms provided a message co-processor with direct access to network FIFOs.