Publications

Hammond, Simon D.; Curry, Matthew J.; Davis, Kevin D.; Dang, Vinh Q.; Guba, Oksana G.; Hoekstra, Robert J.; Laros, James H.; Pedretti, Kevin P.; Poliakoff, David Z.; Rajamanickam, Sivasankaran R.; Trott, Christian R.; Younge, Andrew J.

Abstract not provided.

Hammond, Simon D.; Laros, James H.; Pedretti, Kevin P.; Younge, Andrew J.; Hoekstra, Robert J.

Abstract not provided.

Hughes, Clayton H.; Hammond, Simon D.; Zhang, Mengchi Z.; Liu, Yechen L.; Rogers, Tim R.; Hoekstra, Robert J.

Programmable accelerators have become commonplace in modern computing systems. Advances in programming models and the availability of unprecedented amounts of data have created a space for massively parallel accelerators capable of maintaining context for thousands of concurrent threads resident on-chip. These threads are grouped and interleaved on a cycle-by-cycle basis among several massively parallel computing cores. One path for the design of future supercomputers relies on an ability to model the performance of these massively parallel cores at scale. The SST framework has been proven to scale up to run simulations containing tens of thousands of nodes. A previous report described the initial integration of the open-source, execution-driven GPU simulator, GPGPU-Sim, into the SST framework. This report discusses the results of the integration and how to use the new GPU component in SST. It also provides examples of what it can be used to analyze and a correlation study showing how closely the execution matches that of a Nvidia V100 GPU when running kernels and mini-apps.

Hoekstra, Robert J.; Malone, C.M.; Montoya, D.R.; Ferencz, R.M.; Kuhl, A.L.; Hoekstra, R.J.; Wagner, J.W.

The review was conducted on May 8-9, 2017 at the University of Utah. Overall the review team was impressed with the work presented and found that the CCMSC had met or exceeded the Year 3 milestones. Specific details, comments, and recommendations are included in this document.

International Conference for High Performance Computing, Networking, Storage and Analysis, SC

Pedretti, Kevin P.; Younge, Andrew J.; Hammond, Simon D.; Laros, James H.; Curry, Matthew J.; Aguilar, Michael J.; Hoekstra, Robert J.; Brightwell, Ronald B.

Arm processors have been explored in HPC for several years, however there has not yet been a demonstration of viability for supporting large-scale production workloads. In this paper, we offer a retrospective on the process of bringing up Astra, the first Petascale supercomputer based on 64-bit Arm processors, and validating its ability to run production HPC applications. Through this process several immature technology gaps were addressed, including software stack enablement, Linux bugs at scale, thermal management issues, power management capabilities, and advanced container support. From this experience, several lessons learned are formulated that contributed to the successful deployment of Astra. These insights can be helpful to accelerate deploying and maturing other first-seen HPC technologies. With Astra now supporting many users running a diverse set of production applications at multi-thousand node scales, we believe this constitutes strong supporting evidence that Arm is a viable technology for even the largest-scale supercomputer deployments.

Hoekstra, Robert J.

Abstract not provided.

Hughes, Clayton H.; Hammond, Simon D.; Khairy, Mahmoud K.; Zhang, Mengchi Z.; Green, Roland G.; Rogers, Timothy R.; Hoekstra, Robert J.

Programmable accelerators have become commonplace in modern computing systems. Advances in programming models and the availability of massive amounts of data have created a space for massively parallel accelerators capable of maintaining context for thousands of concurrent threads resident on-chip. These threads are grouped and interleaved on a cycle-by-cycle basis among several massively parallel computing cores. One path for the design of future supercomputers relies on an ability to model the performance of these massively parallel cores at scale. The SST framework has been proven to scale up to run simulations containing tens of thousands of nodes. A previous report described the initial integration of the open-source, execution-driven GPU simulator, GPGPU-Sim, into the SST framework. This report discusses the results of the integration and how to use the new GPU component in SST. It also provides examples of what it can be used to analyze and a correlation study showing how closely the execution matches that of a Nvidia V100 GPU when running kernels and mini-apps.

Hughes, Clayton H.; Hammond, Simon D.; Voskuilen, Gwendolyn R.; Rodrigues, Arun; Hemmert, Karl S.; Hoekstra, Robert J.

Abstract not provided.

Hoekstra, Robert J.; Pedretti, Kevin P.; Hammond, Simon D.; Laros, James H.; Younge, Andrew J.; Lin, Paul L.; Vaughan, Courtney V.

Abstract not provided.

Hammond, Simon D.; Laros, James H.; Pedretti, Kevin P.; Younge, Andrew J.; Vaughan, Courtenay T.; Lin, Paul L.; Hoekstra, Robert J.

Abstract not provided.

Hughes, Clayton H.; Rodrigues, Arun; Voskuilen, Gwendolyn R.; Hemmert, Karl S.; Hammond, Simon D.; Hoekstra, Robert J.

Abstract not provided.

Hughes, Clayton H.; Hammond, Simon D.; Voskuilen, Gwendolyn R.; Rodrigues, Arun; Hemmert, Karl S.; Hoekstra, Robert J.

Abstract not provided.

Khairy, Mahmoud K.; Zhang, Mengchi Z.; Green, Roland G.; Hammond, Simon D.; Hoekstra, Robert J.; Rogers, Timothy R.; Hughes, Clayton H.

Programmable accelerators have become commonplace in modern computing systems. Advances in programming models and the availability of massive amounts of data have created a space for massively parallel acceleration where the context for thousands of concurrent threads are resident on-chip. These threads are grouped and interleaved on a cycle-by-cycle basis among several mas- sively parallel computing cores. The design of future supercomputers relies on an ability to model the performance of these massively parallel cores at scale. To address the need for a scalable, decentralized GPU model that can model large GPUs, chiplet- based GPUs and multi-node GPUs, this report details the first steps in integrating the open-source, execution driven GPGPU-Sim into the SST framework. The first stage of this project, creates two elements: a kernel scheduler SST element accepts work from SST CPU models and schedules it to an SM-collection element that performs cycle-by-cycle timing using SSTs Mem Hierarchy to model a flexible memory system.

Hughes, Clayton H.; Laros, James H.; Pedretti, Kevin P.; Hammond, Simon D.; Younge, Andrew J.; Hoekstra, Robert J.

Abstract not provided.

Hughes, Clayton H.; Laros, James H.; Pedretti, Kevin P.; Hammond, Simon D.; Younge, Andrew J.; Hoekstra, Robert J.

Abstract not provided.

Hoekstra, Robert J.; Bartlett, Roscoe B.; Hammond, Simon D.; Cook, Jeanine C.; Dinge, Dennis D.; Frye, Joseph R.; Hughes, Clayton H.; Lin, Paul L.; Vaughan, Courtenay T.; Hammond, Simon D.

Abstract not provided.

Alvin, Kenneth F.; Laros, James H.; Hoekstra, Robert J.; Collis, Samuel S.; Lujan, Jim L.

Abstract not provided.

Hammond, Simon D.; Laros, James H.; Younge, Andrew J.; Pedretti, Kevin P.; Hoekstra, Robert J.

Abstract not provided.

Hammond, Simon D.; Hoekstra, Robert J.

Abstract not provided.

Laros, James H.; Pedretti, Kevin P.; Hammond, Simon D.; Aguilar, Michael J.; Curry, Matthew L.; Grant, Ryan E.; Hoekstra, Robert J.; Klundt, Ruth A.; Monk, Stephen T.; Ogden, Jeffry B.; Olivier, Stephen L.; Scott, Randall D.; Ward, Harry L.; Younge, Andrew J.

The Vanguard program informally began in January 2017 with the submission of a white pa- per entitled "Sandia's Vision for a 2019 Arm Testbed" to NNSA headquarters. The program proceeded in earnest in May 2017 with an announcement by Doug Wade (Director, Office of Advanced Simulation and Computing and Institutional R&D at NNSA) that Sandia Na- tional Laboratories (Sandia) would host the first Advanced Architecture Prototype platform based on the Arm architecture. In August 2017, Sandia formed a Tri-lab team chartered to develop a robust HPC software stack for Astra to support the Vanguard program goal of demonstrating the viability of Arm in supporting ASC production computing workloads. This document describes the high-level Vanguard program goals, the Vanguard-Astra project acquisition plan and procurement up to contract placement, the initial software stack environment planned for the Vanguard-Astra platform (Astra), a description of how the communities of users will utilize the platform during the transition from the open network to the classified network, and initial performance results.

Laros, James H.; Pedretti, Kevin P.; Hammond, Simon D.; Aguilar, Michael J.; Curry, Matthew L.; Grant, Ryan E.; Hoekstra, Robert J.; Klundt, Ruth A.; Monk, Stephen T.; Ogden, Jeffry B.; Olivier, Stephen L.; Scott, Randall D.; Ward, Harry L.; Younge, Andrew J.

The Vanguard program informally began in January 2017 with the submission of a white pa- per entitled "Sandia's Vision for a 2019 Arm Testbed" to NNSA headquarters. The program proceeded in earnest in May 2017 with an announcement by Doug Wade (Director, Office of Advanced Simulation and Computing and Institutional R&D at NNSA) that Sandia Na- tional Laboratories (Sandia) would host the first Advanced Architecture Prototype platform based on the Arm architecture. In August 2017, Sandia formed a Tri-lab team chartered to develop a robust HPC software stack for Astra to support the Vanguard program goal of demonstrating the viability of Arm in supporting ASC production computing workloads. This document describes the high-level Vanguard program goals, the Vanguard-Astra project acquisition plan and procurement up to contract placement, the initial software stack environment planned for the Vanguard-Astra platform (Astra), a description of how the communities of users will utilize the platform during the transition from the open network to the classified network, and initial performance results.

Hoekstra, Robert J.; Hungerford, Aimee H.; Montoya, David M.; Ferencz, Robert F.; Kuhl, Alan K.; Ruggirello, Kevin P.

Abstract not provided.

Vaughan, Courtenay T.; Cook, Jeanine C.; Benner, R.E.; Dinge, Dennis D.; Lin, Paul L.; Hughes, Clayton H.; Hoekstra, Robert J.; Hammond, Simon D.

Abstract not provided.

Hammond, Simon D.; Rodrigues, Arun; Voskuilen, Gwendolyn R.; Hemmert, Karl S.; Levenhagen, Michael J.; Hughes, Clayton H.; Hoekstra, Robert J.

Abstract not provided.

Vaughan, Courtenay T.; Hammond, Simon D.; Dinge, Dennis D.; Lin, Paul L.; Hughes, Clayton H.; Benner, R.E.; Cook, Jeanine C.; Pase, Douglas M.; Hoekstra, Robert J.

Abstract not provided.