Publications

Aguilar, Michael J.; Pedretti, Kevin P.; Hammond, Simon D.; Laros, James H.; Younge, Andrew J.; Curry, Matthew L.

Abstract not provided.

Khairy, Mahmoud K.; Zhang, Mengchi Z.; Green, Roland G.; Hammond, Simon D.; Hoekstra, Robert J.; Rogers, Timothy R.; Hughes, Clayton H.

Programmable accelerators have become commonplace in modern computing systems. Advances in programming models and the availability of massive amounts of data have created a space for massively parallel acceleration where the context for thousands of concurrent threads are resident on-chip. These threads are grouped and interleaved on a cycle-by-cycle basis among several mas- sively parallel computing cores. The design of future supercomputers relies on an ability to model the performance of these massively parallel cores at scale. To address the need for a scalable, decentralized GPU model that can model large GPUs, chiplet- based GPUs and multi-node GPUs, this report details the first steps in integrating the open-source, execution driven GPGPU-Sim into the SST framework. The first stage of this project, creates two elements: a kernel scheduler SST element accepts work from SST CPU models and schedules it to an SM-collection element that performs cycle-by-cycle timing using SSTs Mem Hierarchy to model a flexible memory system.

Lin, Paul L.; Hammond, Simon D.

Abstract not provided.

Hughes, Clayton H.; Laros, James H.; Pedretti, Kevin P.; Hammond, Simon D.; Younge, Andrew J.; Hoekstra, Robert J.

Abstract not provided.

Hughes, Clayton H.; Laros, James H.; Pedretti, Kevin P.; Hammond, Simon D.; Younge, Andrew J.; Hoekstra, Robert J.

Abstract not provided.

Kommareddy, Vamsee R.; Awad, Amro A.; Hughes, Clayton H.; Hammond, Simon D.

Abstract not provided.

Hoekstra, Robert J.; Bartlett, Roscoe B.; Hammond, Simon D.; Cook, Jeanine C.; Dinge, Dennis D.; Frye, Joseph R.; Hughes, Clayton H.; Lin, Paul L.; Vaughan, Courtenay T.; Hammond, Simon D.

Abstract not provided.

Laros, James H.; Pedretti, Kevin P.; Hammond, Simon D.; Alvin, Kenneth F.

Abstract not provided.

Hammond, Simon D.; Laros, James H.; Younge, Andrew J.; Pedretti, Kevin P.; Hoekstra, Robert J.

Abstract not provided.

Proceedings - 2018 International Conference on High Performance Computing and Simulation, HPCS 2018

Hammond, Simon D.; Vaughan, Courtenay T.; Hughes, Clayton H.

Despite significant advances in the porting of scientific applications to novel architectures such as compute-optimized graphics processors, many-core processor/accelerators and, even special-purpose function units, the vast majority of scientific calculations are still performed on high-performance, commodity server processors. Even in the cases of applications which have been ported to new architectures, frequent serial sections still require strong server-class processor cores to compute as fast as possible. In this paper we report on a set of benchmark studies which evaluate Intel's latest Skylake Xeon server processor. Skylake represents a significant change in the Xeon product line with wider SIMD vector units, a redesigned cache architecture, and, an increased number of memory channels. The wider vector units provide 2x improvement for some compute-intensive applications and the combined memory changes can provide close to 2x the memory bandwidth. We evaluate these new hardware features on several HPC-relevant mini-Applications and benchmarks, including, STREAM, LULESH, XSBench, HPCG and SW4Lite. Together, the new hardware functions provide up to 1.8x speedup on HPC benchmark codes when compared with the previous generation Haswell processor core, providing much greater utility to a broader range of HPC applications that rely on this class of compute node.

Kommareddy, Vamsee R.; Awad, Amro A.; Hughes, Clayton H.; Hammond, Simon D.

Abstract not provided.

Younge, Andrew J.; Laros, James H.; Hammond, Simon D.; Pedretti, Kevin P.

Abstract not provided.

Laros, James H.; Pedretti, Kevin P.; Hammond, Simon D.

Abstract not provided.

Levenhagen, Michael J.; Hammond, Simon D.; Hemmert, Karl S.

Abstract not provided.

Hammond, Simon D.; Hoekstra, Robert J.

Abstract not provided.

Laros, James H.; Pedretti, Kevin P.; Hammond, Simon D.; Aguilar, Michael J.; Curry, Matthew L.; Grant, Ryan E.; Hoekstra, Robert J.; Klundt, Ruth A.; Monk, Stephen T.; Ogden, Jeffry B.; Olivier, Stephen L.; Scott, Randall D.; Ward, Harry L.; Younge, Andrew J.

The Vanguard program informally began in January 2017 with the submission of a white pa- per entitled "Sandia's Vision for a 2019 Arm Testbed" to NNSA headquarters. The program proceeded in earnest in May 2017 with an announcement by Doug Wade (Director, Office of Advanced Simulation and Computing and Institutional R&D at NNSA) that Sandia Na- tional Laboratories (Sandia) would host the first Advanced Architecture Prototype platform based on the Arm architecture. In August 2017, Sandia formed a Tri-lab team chartered to develop a robust HPC software stack for Astra to support the Vanguard program goal of demonstrating the viability of Arm in supporting ASC production computing workloads. This document describes the high-level Vanguard program goals, the Vanguard-Astra project acquisition plan and procurement up to contract placement, the initial software stack environment planned for the Vanguard-Astra platform (Astra), a description of how the communities of users will utilize the platform during the transition from the open network to the classified network, and initial performance results.

Laros, James H.; Pedretti, Kevin P.; Hammond, Simon D.; Aguilar, Michael J.; Curry, Matthew L.; Grant, Ryan E.; Hoekstra, Robert J.; Klundt, Ruth A.; Monk, Stephen T.; Ogden, Jeffry B.; Olivier, Stephen L.; Scott, Randall D.; Ward, Harry L.; Younge, Andrew J.

The Vanguard program informally began in January 2017 with the submission of a white pa- per entitled "Sandia's Vision for a 2019 Arm Testbed" to NNSA headquarters. The program proceeded in earnest in May 2017 with an announcement by Doug Wade (Director, Office of Advanced Simulation and Computing and Institutional R&D at NNSA) that Sandia Na- tional Laboratories (Sandia) would host the first Advanced Architecture Prototype platform based on the Arm architecture. In August 2017, Sandia formed a Tri-lab team chartered to develop a robust HPC software stack for Astra to support the Vanguard program goal of demonstrating the viability of Arm in supporting ASC production computing workloads. This document describes the high-level Vanguard program goals, the Vanguard-Astra project acquisition plan and procurement up to contract placement, the initial software stack environment planned for the Vanguard-Astra platform (Astra), a description of how the communities of users will utilize the platform during the transition from the open network to the classified network, and initial performance results.

ACM International Conference Proceeding Series

Butcher, Neil; Olivier, Stephen L.; Berry, Jonathan W.; Hammond, Simon D.; Kogge, Peter M.

Technologies such as Multi-Channel DRAM (MCDRAM) or High Bandwidth Memory (HBM) provide significantly more bandwidth than conventional memory. This trend has raised questions about how applications should manage data transfers between levels. This paper focuses on evaluating different usage modes of the MCDRAM in Intel Knights Landing (KNL) manycore processors. We evaluate these usage modes with a sorting kernel and a sorting-based streaming benchmark. We develop a performance model for the benchmark and use experimental evidence to demonstrate the correctness of the model. The model projects near-optimal numbers of copy threads for memory bandwidth bound computations. We demonstrate on KNL up to a 1.9X speedup for sort when the problem does not fit in MCDRAM over an OpenMP GNU sort that does not use MCDRAM.

Berry, Jonathan W.; Butcher, Neil; Olivier, Stephen L.; Hammond, Simon D.; Kogge, Peter M.

Abstract not provided.

Kommareddy, Vamsee R.; Hughes, Clayton H.; Hammond, Simon D.; Awad, Amro A.

Many modern applications have memory footprints that are increasingly large, driving system memory capacities higher and higher. Moreover, these systems are often organized where the bulk of the memory is collocated with the compute capability, which necessitates the need for message passing APIs to facilitate information sharing between compute nodes. Due to the diversity of applications that must run on High-Performance Computing (HPC) systems, the memory utiliza- tion can fluctuate wildly from one application to another. And, because memory is located in the node, maintenance can become problematic because each node must be taken offline and upgraded individually. To address these issues, vendors are exploring disaggregated, memory-centric, systems. In this type of organization, there are discrete nodes,reserved solely for memory, which are shared across many compute nodes. Due to their capacity, low-power, and non-volatility, Non-Volatile Memories (NVMs) are ideal candidates for these memory nodes. This report discusses a new component for the Structural Simulation Toolkit (SST), Opal, that can be used to study the impact of using NVMs in a disaggregated system in terms of performance, security, and memory management. This page intentionally left blank.

Lacy, Susan L.; Noe, John P.; Ogden, Jeffry B.; Hammond, Simon D.

Abstract not provided.

Hughes, Clayton H.; Vaughan, Courtenay T.; Hammond, Simon D.

Abstract not provided.

Younge, Andrew J.; Pedretti, Kevin P.; Laros, James H.; Hammond, Simon D.

Abstract not provided.

Brandt, James M.; Gentile, Ann C.; Hammond, Simon D.; Cook, Jeanine C.; Allan, Benjamin A.; Tucker, Thomas T.; Naksinehaboon, Nichamon N.; Taerat, Narate T.; Cook, Jonathan C.; Aaziz, Omar R.; Ates, Emre A.; Tuncer, Ozan T.; Egele, Manuel E.; Turk, Ata T.; Coskun, Ayse K.; izadpanah, ramin i.; Dechev, Damian D.

Abstract not provided.

Hammond, Simon D.; Trott, Christian R.; Ibanez-Granados, Daniel A.; Sunderland, Daniel S.

Abstract not provided.