Publications

Vaughan, Courtenay T.; Cook, Jeanine C.; Benner, R.E.; Dinge, Dennis D.; Lin, Paul L.; Hughes, Clayton H.; Hoekstra, Robert J.; Hammond, Simon D.

Abstract not provided.

Vaughan, Courtenay T.; Hammond, Simon D.; Dinge, Dennis D.; Lin, Paul L.; Hughes, Clayton H.; Benner, R.E.; Cook, Jeanine C.; Pase, Douglas M.; Hoekstra, Robert J.

Abstract not provided.

Proceedings - International Symposium on High-Performance Computer Architecture

Srikanth, Sriseshan; Rabbat, Paul G.; Hein, Eric R.; Deng, Bobin; Conte, Thomas M.; DeBenedictis, Erik; Cook, Jeanine C.; Frank, Michael P.

Dennard scaling ended a decade ago. Energy reduction by lowering supply voltage has been limited because of guard bands and a subthreshold slope of over 60mV/decade in MOSFETs. On the other hand, newly-proposed logic devices maintain a high on/off ratio for drain currents even at significantly lower operating voltages. However, such ultra low power technology would eventually suffer from intermittent errors in logic as a result of operating close to the thermal noise floor. Computational error correction mitigates this issue by efficiently correcting stochastic bit errors that may occur in computational logic operating at low signal energies, thereby allowing for energy reduction by lowering supply voltage to tens of millivolts. Cores based on a Redundant Residual Number System (RRNS), which represents a number using a tuple of smaller numbers, are a promising candidate for implementing energyefficient computational error correction. However, prior RRNS core microarchitectures abstract away the memory hierarchy and do not consider the power-performance impact of RNS-based memory addressing. When compared with a non-error-correcting core addressing memory in binary, naive RNS-based memory addressing schemes cause a slowdown of over 3x/2x for inorder/out-of-order cores respectively. In this paper, we analyze RNS-based memory access pattern behavior and provide solutions in the form of novel schemes and the resulting design space exploration, thereby, extending and enabling a tangible, ultra low power RRNS based architecture.

Brandt, James M.; Gentile, Ann C.; Cook, Jonathan E.; Allan, Benjamin A.; Cook, Jeanine C.; Aaziz, Omar R.; Tucker, Thomas T.; Nichamon, Naksinehaboon N.; Taerat, Narate T.; Ates, Emre A.; Tuncer, Ozan T.; Egele, Manuel E.; Turk, Ata T.; Coskun, Ayse K.

Abstract not provided.

Hammond, Simon D.; Trott, Christian R.; Ibanez-Granados, Daniel A.; Edwards, Harold C.; Sunderland, Daniel S.; Ellingwood, Nathan D.; Brandt, James M.; Gentile, Ann C.; Cook, Jeanine C.; Hoekstra, Robert J.

Abstract not provided.

Brandt, James M.; Hammond, Simon D.; Tucker, Thomas T.; Gentile, Ann C.; Cook, Jeanine C.

Abstract not provided.

Hammond, Simon D.; Vaughan, Courtenay T.; Dinge, Dennis D.; Lin, Paul L.; Benner, R.E.; Hughes, Clayton H.; Trott, Christian R.; Cook, Jeanine C.; Hoekstra, Robert J.

Abstract not provided.

Cook, Jeanine C.

Continued progress in computing has augmented the quest for higher performance with a new quest for higher energy efficiency. This has led to the re-emergence of Processing-In-Memory (PIM) ar- chitectures that offer higher density and performance with some boost in energy efficiency. Past PIM work either integrated a standard CPU with a conventional DRAM to improve the CPU- memory link, or used a bit-level processor with Single Instruction Multiple Data (SIMD) control, but neither matched the energy consumption of the memory to the computation. We originally proposed to develop a new architecture derived from PIM that more effectively addressed energy efficiency for high performance scientific, data analytics, and neuromorphic applications. We also originally planned to implement a von Neumann architecture with arithmetic/logic units (ALUs) that matched the power consumption of an advanced storage array to maximize energy efficiency. Implementing this architecture in storage was our original idea, since by augmenting storage (in- stead of memory), the system could address both in-memory computation and applications that accessed larger data sets directly from storage, hence Processing-in-Memory-and-Storage (PIMS). However, as our research matured, we discovered several things that changed our original direc- tion, the most important being that a PIM that implements a standard von Neumann-type archi- tecture results in significant energy efficiency improvement, but only about a O(10) performance improvement. In addition to this, the emergence of new memory technologies moved us to propos- ing a non-von Neumann architecture, called Superstrider, implemented not in storage, but in a new DRAM technology called High Bandwidth Memory (HBM). HBM is a stacked DRAM tech- nology that includes a logic layer where an architecture such as Superstrider could potentially be implemented.

DeBenedictis, Erik; Srikanth, Sriseshan S.; Cook, Jeanine C.; Conte, Thomas M.

Abstract not provided.

Srikanth, Sriseshan S.; DeBenedictis, Erik; Cook, Jeanine C.; Conte, Thomas M.

Abstract not provided.

DeBenedictis, Erik; Cook, Jeanine C.; Srikanth, Sriseshan S.; Conte, Thomas M.

Abstract not provided.

Siddique, Nafiul S.; Badawy, Hameed B.; Cook, Jeanine C.

Abstract not provided.

DeBenedictis, Erik; Cook, Jeanine C.; Srikanth, Sriseshan S.; Conte, Thomas M.

Abstract not provided.

Vaughan, Courtenay T.; Hammond, Simon D.; Dinge, Dennis D.; Lin, Paul L.; Pase, Douglas M.; Cook, Jeanine C.; Trott, Christian R.; Hughes, Clayton H.; Hoekstra, Robert J.

Abstract not provided.

Vaughan, Courtenay T.; Hammond, Simon D.; Dinge, Dennis D.; Lin, Paul L.; Pase, Douglas M.; Trott, Christian R.; Cook, Jeanine C.; Hughes, Clayton H.; Hoekstra, Robert J.

Abstract not provided.

DeBenedictis, Erik; Cook, Jeanine C.; Srikanth, Sriseshan S.

Abstract not provided.

Vaughan, Courtenay T.; Dinge, Dennis D.; Lin, Paul L.; Hammond, Simon D.; Pase, Douglas M.; Benner, Douglas E.; Cook, Jeanine C.; Hoekstra, Robert J.

Abstract not provided.

Hammond, Simon D.; Trott, Christian R.; Vaughan, Courtenay T.; Dinge, Dennis D.; Lin, Paul L.; Pase, Douglas M.; Benner, R.E.; Cook, Jeanine C.; Hoekstra, Robert J.

Abstract not provided.

Hammond, Simon D.; Vaughan, Courtenay T.; Dinge, Dennis D.; Lin, Paul L.; Pase, Douglas M.; Cook, Jeanine C.; Hoekstra, Robert J.

Abstract not provided.

2016 IEEE International Conference on Rebooting Computing, ICRC 2016 - Conference Proceedings

Agarwal, Sapan A.; Cook, Jeanine C.; DeBenedictis, Erik; Frank, Michael P.; Cauwenberghs, Gert; Srikanth, Sriseshan; Deng, Bobin; Hein, Eric R.; Rabbat, Paul G.; Conte, Thomas M.

We address practical limits of energy efficiency scaling for logic and memory. Scaling of logic will end with unreliable operation, making computers probabilistic as a side effect. The errors can be corrected or tolerated, but overhead will increase with further scaling. We address the tradeoff between scaling and error correction that yields minimum energy per operation, finding new error correction methods with energy consumption limits about 2× below current approaches. The maximum energy efficiency for memory depends on several other factors. Adiabatic and reversible methods applied to logic have promise, but overheads have precluded practical use. However, the regular array structure of memory arrays tends to reduce overhead and makes adiabatic memory a viable option. This paper reports an adiabatic memory that has been tested at about 85× improvement over standard designs for energy efficiency. Combining these approaches could set energy efficiency expectations for processor-in-memory computing systems.

Hammond, Simon D.; Trott, Christian R.; Lin, Paul L.; Vaughan, Courtenay T.; Cook, Jeanine C.; Dinge, Dennis D.; Pase, Douglas M.; Benner, R.E.; Hoekstra, Robert J.

Abstract not provided.

Agarwal, Sapan A.; Cook, Jeanine C.; DeBenedictis, Erik; Frank, Michael P.; Cauwenburghs, Gert C.; Srikanth, Sriseshan S.; Deng, Bobin D.; Hein, Eric R.; Rabbat, Paul R.; Conte, Thomas M.

Abstract not provided.

Ang, James A.; Barrett, Richard F.; Benner, R.E.; Burke, Daniel B.; Chan, Cy P.; Cook, Jeanine C.; Daley, Christopher D.; Donofrio, Dave D.; Hammond, Simon D.; Hemmert, Karl S.; Hoekstra, Robert J.; Ibrahim, Khaled I.; Kelly, Suzanne M.; Le, Hoang L.; Leung, Vitus J.; Michelogiannakis, George M.; Resnick, David R.; Rodrigues, Arun; Shalf, John S.; Stark, Dylan S.; Unat, D.U.; Wright, Nick W.; Voskuilen, Gwendolyn R.

Machine Models and Proxy Architectures for Exascale Computing Version 2.0 Prepared by Sandia National Laboratories Albuquerque, New Mexico 87185 and Livermore, California 94550 Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000. Approved for public release; further dissemination unlimited. Issued by Sandia National Laboratories, operated for the United States Department of Energy by Sandia Corporation. NOTICE: This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government, nor any agency thereof, nor any of their employees, nor any of their contractors, subcontractors, or their employees, make any warranty, express or implied, or assume any legal liability or responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or rep- resent that its use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government, any agency thereof, or any of their contractors or subcontractors. The views and opinions expressed herein do not necessarily state or reflect those of the United States Government, any agency thereof, or any of their contractors. Printed in the United States of America. This report has been reproduced directly from the best available copy. Available to DOE and DOE contractors from U.S. Department of Energy Office of Scientific and Technical Information P.O. Box 62 Oak Ridge, TN 37831 Telephone: (865) 576-8401 Facsimile: (865) 576-5728 E-Mail: reports@adonis.osti.gov Online ordering: http://www.osti.gov/bridge Available to the public from U.S. Department of Commerce National Technical Information Service 5285 Port Royal Rd Springfield, VA 22161 Telephone: (800) 553-6847 Facsimile: (703) 605-6900 E-Mail: orders@ntis.fedworld.gov Online ordering: http://www.ntis.gov/help/ordermethods.asp?loc=7-4-0#online D E P A R T M E N T O F E N E R G Y * * U N I T E D S T A T E S O F A M E R I C A SAND2016-6049 Unlimited Release Printed Abstract Machine Models and Proxy Architectures for Exascale Computing Version 2.0 J.A. Ang 1 , R.F. Barrett 1 , R.E. Benner 1 , D. Burke 2 , C. Chan 2 , J. Cook 1 , C.S. Daley 2 , D. Donofrio 2 , S.D. Hammond 1 , K.S. Hemmert 1 , R.J. Hoekstra 1 , K. Ibrahim 2 , S.M. Kelly 1 , H. Le, V.J. Leung 1 , G. Michelogiannakis 2 , D.R. Resnick 1 , A.F. Rodrigues 1 , J. Shalf 2 , D. Stark, D. Unat, N.J. Wright 2 , G.R. Voskuilen 1 1 1 Sandia National Laboratories, P.O. Box 5800, Albuquerque, New Mexico 87185-MS 1319 2 Lawrence Berkeley National Laboratory, Berkeley, California Abstract To achieve exascale computing, fundamental hardware architectures must change. The most sig- nificant consequence of this assertion is the impact on the scientific and engineering applications that run on current high performance computing (HPC) systems, many of which codify years of scientific domain knowledge and refinements for contemporary computer systems. In order to adapt to exascale architectures, developers must be able to reason about new hardware and deter- mine what programming models and algorithms will provide the best blend of performance and energy efficiency into the future. While many details of the exascale architectures are undefined, an abstract machine model is designed to allow application developers to focus on the aspects of the machine that are important or relevant to performance and code structure. These models are intended as communication aids between application developers and hardware architects during the co-design process. We use the term proxy architecture to describe a parameterized version of an abstract machine model, with the parameters added to elucidate potential speeds and capacities of key hardware components. These more detailed architectural models are formulated to enable discussion between the developers of analytic models and simulators and computer hardware archi- tects. They allow for application performance analysis and hardware optimization opportunities. In this report our goal is to provide the application development community with a set of mod- els that can help software developers prepare for exascale. In addition, through the use of proxy architectures, we can enable a more concrete exploration of how well new and evolving applica- tion codes map onto future architectures. This second version of the document addresses system scale considerations and provides a system-level abstract machine model with proxy architecture information.

Vaughan, Courtenay T.; Dinge, Dennis D.; Lin, Paul L.; Hammond, Simon D.; Cook, Jeanine C.; Trott, Christian R.; Agelastos, Anthony M.; Pase, Douglas M.; Benner, R.E.; Rajan, Mahesh R.; Hoekstra, Robert J.

Abstract not provided.

Vaughan, Courtenay T.; Dinge, Dennis D.; Lin, Paul L.; Hammond, Simon D.; Cook, Jeanine C.; Trott, Christian R.; Agelastos, Anthony M.; Pase, Douglas M.; Benner, R.E.; Rajan, Mahesh R.; Hoekstra, Robert J.; Pierson, Kendall H.

Abstract not provided.