Publications

Kommareddy, Vamsee R.; Awad, Amro A.; Hughes, Clayton H.; Hammond, Simon D.

Abstract not provided.

Hoekstra, Robert J.; Bartlett, Roscoe B.; Hammond, Simon D.; Cook, Jeanine C.; Dinge, Dennis D.; Frye, Joseph R.; Hughes, Clayton H.; Lin, Paul L.; Vaughan, Courtenay T.; Hammond, Simon D.

Abstract not provided.

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Ye, Mao; Hughes, Clayton H.; Awad, Amro

With Non-Volatile Memories (NVMs) beginning to enter the mainstream computing market, it is time to consider how to secure NVM-equipped computing systems. Recent Meltdown and Spectre attacks are evidence that security must be intrinsic to computing systems and not added as an afterthought. Processor vendors are taking the first steps and are beginning to build security primitives into commodity processors. One security primitive that is associated with the use of emerging NVMs is memory encryption. Memory encryption, while necessary, is very challenging when used with NVMs because it exacerbates the write endurance problem. Secure architectures use cryptographic metadata that must be persisted and restored to allow secure recovery of data in the event of power-loss. Specifically, encryption counters must be persistent to enable secure and functional recovery of an interrupted system. However, the cost of ensuring and maintaining persistence for these counters can be significant. In this paper, we propose a novel scheme to maintain encryption counters without the need for frequent updates. Our new memory controller design, Osiris, repurposes memory Error-Correction Codes (ECCs) to enable fast restoration and recovery of encryption counters. To evaluate our design, we use Gem5 to run eight memory-intensive workloads selected from SPEC2006 and U.S. Department of Energy (DoE) proxy applications. Compared to a write-Through counter-cache scheme, on average, Osiris can reduce 48.7% of the memory writes (increase lifetime by 1.95x), and reduce the performance overhead from 51.5% (for write-Through) to only 5.8%. Furthermore, without the need for backup battery or extra power-supply hold-up time, Osiris performs better than a battery-backed write-back (5.8% vs. 6.6% overhead) and has less write-Traffic (2.6% vs. 5.9% overhead).

Proceedings - 2018 International Conference on High Performance Computing and Simulation, HPCS 2018

Hammond, Simon D.; Vaughan, Courtenay T.; Hughes, Clayton H.

Despite significant advances in the porting of scientific applications to novel architectures such as compute-optimized graphics processors, many-core processor/accelerators and, even special-purpose function units, the vast majority of scientific calculations are still performed on high-performance, commodity server processors. Even in the cases of applications which have been ported to new architectures, frequent serial sections still require strong server-class processor cores to compute as fast as possible. In this paper we report on a set of benchmark studies which evaluate Intel's latest Skylake Xeon server processor. Skylake represents a significant change in the Xeon product line with wider SIMD vector units, a redesigned cache architecture, and, an increased number of memory channels. The wider vector units provide 2x improvement for some compute-intensive applications and the combined memory changes can provide close to 2x the memory bandwidth. We evaluate these new hardware features on several HPC-relevant mini-Applications and benchmarks, including, STREAM, LULESH, XSBench, HPCG and SW4Lite. Together, the new hardware functions provide up to 1.8x speedup on HPC benchmark codes when compared with the previous generation Haswell processor core, providing much greater utility to a broader range of HPC applications that rely on this class of compute node.

Kommareddy, Vamsee R.; Awad, Amro A.; Hughes, Clayton H.; Hammond, Simon D.

Abstract not provided.

Kommareddy, Vamsee R.; Hughes, Clayton H.; Hammond, Simon D.; Awad, Amro A.

Many modern applications have memory footprints that are increasingly large, driving system memory capacities higher and higher. Moreover, these systems are often organized where the bulk of the memory is collocated with the compute capability, which necessitates the need for message passing APIs to facilitate information sharing between compute nodes. Due to the diversity of applications that must run on High-Performance Computing (HPC) systems, the memory utiliza- tion can fluctuate wildly from one application to another. And, because memory is located in the node, maintenance can become problematic because each node must be taken offline and upgraded individually. To address these issues, vendors are exploring disaggregated, memory-centric, systems. In this type of organization, there are discrete nodes,reserved solely for memory, which are shared across many compute nodes. Due to their capacity, low-power, and non-volatility, Non-Volatile Memories (NVMs) are ideal candidates for these memory nodes. This report discusses a new component for the Structural Simulation Toolkit (SST), Opal, that can be used to study the impact of using NVMs in a disaggregated system in terms of performance, security, and memory management. This page intentionally left blank.

Hughes, Clayton H.; Vaughan, Courtenay T.; Hammond, Simon D.

Abstract not provided.

Vaughan, Courtenay T.; Cook, Jeanine C.; Benner, R.E.; Dinge, Dennis D.; Lin, Paul L.; Hughes, Clayton H.; Hoekstra, Robert J.; Hammond, Simon D.

Abstract not provided.

Hammond, Simon D.; Rodrigues, Arun; Voskuilen, Gwendolyn R.; Hemmert, Karl S.; Levenhagen, Michael J.; Hughes, Clayton H.; Hoekstra, Robert J.

Abstract not provided.

Vaughan, Courtenay T.; Hammond, Simon D.; Dinge, Dennis D.; Lin, Paul L.; Hughes, Clayton H.; Benner, R.E.; Cook, Jeanine C.; Pase, Douglas M.; Hoekstra, Robert J.

Abstract not provided.

Hammond, Simon D.; Hughes, Clayton H.; Awad, Amro A.; Voskuilen, Gwendolyn R.; Rodrigues, Arun; Hemmert, Karl S.; Levenhagen, Michael J.; Hoekstra, Robert J.

Abstract not provided.

Hughes, Clayton H.; Awad, Amro A.; Hammond, Simon D.; Rodrigues, Arun; Hemmert, Karl S.; Hoekstra, Robert J.

Abstract not provided.

Hammond, Simon D.; Vaughan, Courtenay T.; Dinge, Dennis D.; Lin, Paul L.; Benner, R.E.; Hughes, Clayton H.; Trott, Christian R.; Cook, Jeanine C.; Hoekstra, Robert J.

Abstract not provided.

Hammond, Simon D.; Rodrigues, Arun; Hemmert, Karl S.; Voskuilen, Gwendolyn R.; Hughes, Clayton H.; Levenhagen, Michael J.; Hoekstra, Robert J.; Ang, James A.

Abstract not provided.

ACM International Conference Proceeding Series

Awad, Amro A.; Hammond, Simon D.; Hughes, Clayton H.; Rodrigues, Arun; Hemmert, Karl S.; Hoekstra, Robert J.

DRAM scalability is becoming more challenging, pushing the focus of the research community towards alternative memory technologies. Many emerging non-volatile memory (NVM) devices are proving themselves to be good candidates to replace DRAM in the coming years. For example, the recently announced 3D-XPoint memory by Intel/Micron promises latencies that are comparable to DRAM, while being non-volatile and much more dense. While emerging NVMs can be fabricated in different form factors, the most promising (from a performance perspective) are NVM-based DIMMs. Unfortunately, there is a shortage of studies that explore the design options for NVM-based DIMMs. Because of the read and write asymmetries in both power consumption and latency, as well as limited write endurance, which often requires wear-leveling techniques, NVMs require a specialized controller. The fact that future on-die memory controllers are expected to handle different memory technologies pushes future hardware towards on-DIMM controllers. In this paper, we propose an architectural model for NVM-based DIMMs with internal controllers, explore their design space, evaluate different optimizations and reach out to several architectural suggestions. Finally, we make our model publicly available and integrate it with a widely used architectural simulator.

Awad, Amro A.; Hammond, Simon D.; Hughes, Clayton H.; Rodrigues, Arun; Hemmert, Karl S.; Hoekstra, Robert J.

Abstract not provided.

Vaughan, Courtenay T.; Hammond, Simon D.; Dinge, Dennis D.; Lin, Paul L.; Pase, Douglas M.; Cook, Jeanine C.; Trott, Christian R.; Hughes, Clayton H.; Hoekstra, Robert J.

Abstract not provided.

Vaughan, Courtenay T.; Hammond, Simon D.; Dinge, Dennis D.; Lin, Paul L.; Pase, Douglas M.; Trott, Christian R.; Cook, Jeanine C.; Hughes, Clayton H.; Hoekstra, Robert J.

Abstract not provided.

Awad, Amro A.; Voskuilen, Gwendolyn R.; Rodrigues, Arun; Hammond, Simon D.; Hoekstra, Robert J.; Hughes, Clayton H.

DRAM technology is the main building block of main memory, however, DRAM scaling is becoming very challenging. The main issues for DRAM scaling are the increasing error rates with each new generation, the geometric and physical constraints of scaling the capacitor part of the DRAM cells, and the high power consumption caused by the continuous need for refreshing cell values. At the same time, emerging Non- Volatile Memory (NVM) technologies, such as Phase-Change Memory (PCM), are emerging as promising replacements for DRAM. NVMs, when compared to current technologies e.g., NAND-based ash, have latencies comparable to DRAM. Additionally, NVMs are non-volatile, which eliminates the need for refresh power and enables persistent memory applications. Finally, NVMs have promising densities and the potential for multi-level cell (MLC) storage.