Publications
Assessing the predictive capabilities of mini-applications
Abstract not provided.
Sandia's Appro %22Compton%22Cluster
Abstract not provided.
Unprecedented Scalability and Performance of the new NNSA Tri-Lab Capacity Cluster 2 (TLCC2)
Abstract not provided.
Early Experiences with Co-Design
Abstract not provided.
Unprecedented Scalability and Performance of the new NNSA Tri-Lab Capacity Cluster 2 (TLCC2)
Abstract not provided.
Early Experiences with Intel MIC Architecture
Abstract not provided.
Towards Automated Memory Model Generation Via Event Tracing
Computer Journal
The importance of memory performance and capacity is a growing concern for high performance computing laboratories around the world. It has long been recognized that improvements in processor speed exceed the rate of improvement in dynamic random access memory speed and, as a result, memory access times can be the limiting factor in high performance scientific codes. The use of multi-core processors exacerbates this problem with the rapid growth in the number of cores not being matched by similar improvements in memory capacity, increasing the likelihood of memory contention. In this paper, we present WMTools , a lightweight memory tracing tool and analysis framework for parallel codes, which is able to identify peak memory usage and also analyse per-function memory use over time. An evaluation of WMTools , in terms of its effectiveness and also its overheads, is performed using nine established scientific applications/benchmark codes representing a variety of programming languages and scientific domains. We also show how WMTools can be used to automatically generate a parameterized memory model for one of these applications, a two-dimensional non-linear magnetohydrodynamics application, Lare2D . Through the memory model we are able to identify an unexpected growth term which becomes dominant at scale. With a refined model we are able to predict memory consumption with under 7% error.
Sandia previews initial mini-application ports to AMD's next generation Trinity APU and Tahiti Southern Island GPU Technologies
Abstract not provided.
Early Experiences with Heterogeneous Compute
Abstract not provided.
Early Experiences with Intel MIC Architcture
Abstract not provided.
Navigating An Evolutionary Fast Path to Exascale
Exascale Design Space Exploration and Co-design
Proposed for publication in Future Generation Computer Systems.
Abstract not provided.
Parallel File System Analysis Through Application I/O Tracing
The Computer Journal
Abstract not provided.
LDPLFS: Improving I/O Performance Without Application Modification
Abstract not provided.
Coarse-Grain Simulation of Networks-on-Chip using SST/Macro
Abstract not provided.