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Three-dimensional fully-coupled electrical and thermal transport model of dynamic switching in oxide memristors

ECS Transactions (Online)

Gao, Xujiao G.; Mamaluy, Denis M.; Mickel, Patrick R.; Marinella, Matthew J.

In this paper, we present a fully-coupled electrical and thermal transport model for oxide memristors that solves simultaneously the time-dependent continuity equations for all relevant carriers, together with the time-dependent heat equation including Joule heating sources. The model captures all the important processes that drive memristive switching and is applicable to simulate switching behavior in a wide range of oxide memristors. The model is applied to simulate the ON switching in a 3D filamentary TaOx memristor. Simulation results show that, for uniform vacancy density in the OFF state, vacancies fill in the conduction filament till saturation, and then fill out a gap formed in the Ta electrode during ON switching; furthermore, ON-switching time strongly depends on applied voltage and the ON-to-OFF current ratio is sensitive to the filament vacancy density in the OFF state.

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The fundamental downscaling limit of field effect transistors

Applied Physics Letters

Mamaluy, Denis M.; Gao, Xujiao G.

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.

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Three-dimensional fully-coupled electrical and thermal transport model of dynamic switching in oxide memristors

ECS Transactions

Gao, Xujiao G.; Mamaluy, Denis M.; Mickel, P.R.; Marinella, M.

We present a fully-coupled electrical and thermal transport model for oxide memristors that solves simultaneously the time-dependent continuity equations for all relevant carriers, together with the time-dependent heat equation including Joule heating sources. The model captures all the important processes that drive memristive switching, and is applicable to simulate switching behavior in a wide range of oxide memristors. The model is applied to simulate the ON switching in a 3D filamentary TaOx memristor. Simulation results show that, for uniform vacancy density in the OFF state, vacancies fill in the conduction filament till saturation, and then fill out a gap formed in the Ta electrode during ON switching; furthermore, ON-switching time strongly depends on applied voltage and the ON-to-OFF current ratio is sensitive to the filament vacancy density in the OFF state.

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The ultimate downscaling limit of FETs

Mamaluy, Denis M.; Gao, Xujiao G.; Tierney, Brian D.

We created a highly efficient, universal 3D quant um transport simulator. We demonstrated that the simulator scales linearly - both with the problem size (N) and number of CPUs, which presents an important break-through in the field of computational nanoelectronics. It allowed us, for the first time, to accurately simulate and optim ize a large number of realistic nanodevices in a much shorter time, when compared to other methods/codes such as RGF[%7EN 2.333 ]/KNIT, KWANT, and QTBM[%7EN 3 ]/NEMO5. In order to determine the best-in-class for different beyond-CMOS paradigms, we performed rigorous device optimization for high-performance logic devices at 6-, 5- and 4-nm gate lengths. We have discovered that there exists a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs). We have found that, at room temperatures, all FETs, irre spective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths.

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Development characterization and modeling of a TaOx ReRAM for a neuromorphic accelerator

Marinella, Matthew J.; Mickel, Patrick R.; Lohn, Andrew L.; Hughart, David R.; Bondi, Robert J.; Mamaluy, Denis M.; Hjalmarson, Harold P.; Stevens, James E.; Decker, Seth D.; Apodaca, Roger A.; Evans, Brian R.; Aimone, James B.; Rothganger, Fredrick R.; James, Conrad D.; DeBenedictis, Erik

This report discusses aspects of neuromorphic computing and how it is used to model microsystems.

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Results 26–37 of 37
Results 26–37 of 37