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Reversible computing with fast, fully static, fully adiabatic CMOS

Proceedings - 2020 International Conference on Rebooting Computing, ICRC 2020

Frank, Michael P.; Brocato, Robert W.; Tierney, Brian D.; Missert, Nancy A.; Hsia, Alexander H.

To advance the energy efficiency of general digital computing far beyond the thermodynamic limits that apply to conventional digital circuits will require utilizing the principles of reversible computing. It has been known since the early 1990s that reversible computing based on adiabatic switching is possible in CMOS, although almost all the “adiabatic” CMOS logic families in the literature are not actually fully adiabatic, which limits their achievable energy savings. The first CMOS logic style achieving truly, fully adiabatic operation if leakage was negligible (CRL) was not fully static, which led to practical engineering difficulties in the presence of certain nonidealities. Later, “static” adiabatic logic families were described, but they were not actually fully adiabatic, or fully static, and were much slower. In this paper, we describe a new logic family, Static 2-Level Adiabatic Logic (S2LAL), which is, to our knowledge, the first CMOS logic family that is both fully static, and truly, fully adiabatic (modulo leakage). In addition, S2LAL is, we think, the fastest possible such family (among fully pipelined sequential circuits), having a latency per logic stage of one tick (transition time), and a minimum clock period (initiation interval) of 8 ticks. S2LAL requires 8 phases of a trapezoidal power-clock waveform (plus constant power and ground references) to be supplied. We argue that, if implemented in a suitable fabrication process designed to aggressively minimize leakage, S2LAL should be capable of demonstrating a greater level of energy efficiency than any other semiconductor-based digital logic family known today.

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Fully-Coupled Thermo-Electrical Modeling and Simulation of Transition Metal Oxide Memristors

Mamaluy, Denis M.; Gao, Xujiao G.; Tierney, Brian D.

Transition metal oxide (TMO) memristors have recently attracted special attention from the semiconductor industry and academia. Memristors are one of the strongest candidates to replace flash memory, and possibly DRAM and SRAM in the near future. Moreover, memristors have a high potential to enable beyond-CMOS technology advances in novel architectures for high performance computing (HPC). The utility of memristors has been demonstrated in reprogrammable logic (cross-bar switches), brain-inspired computing and in non-CMOS complementary logic. Indeed, the potential use of memristors as logic devices is especially important considering the inevitable end of CMOS technology scaling that is anticipated by 2025. In order to aid the on-going Sandia memristor fabrication effort with a memristor design tool and establish a clear physical picture of resistance switching in TMO memristors, we have created and validated with experimental data a simulation tool we name the Memristor Charge Transport (MCT) Simulator.

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The ultimate downscaling limit of FETs

Mamaluy, Denis M.; Gao, Xujiao G.; Tierney, Brian D.

We created a highly efficient, universal 3D quant um transport simulator. We demonstrated that the simulator scales linearly - both with the problem size (N) and number of CPUs, which presents an important break-through in the field of computational nanoelectronics. It allowed us, for the first time, to accurately simulate and optim ize a large number of realistic nanodevices in a much shorter time, when compared to other methods/codes such as RGF[%7EN 2.333 ]/KNIT, KWANT, and QTBM[%7EN 3 ]/NEMO5. In order to determine the best-in-class for different beyond-CMOS paradigms, we performed rigorous device optimization for high-performance logic devices at 6-, 5- and 4-nm gate lengths. We have discovered that there exists a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs). We have found that, at room temperatures, all FETs, irre spective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths.

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6 Results
6 Results