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As part of NNSA’s Advanced Simulation and Computing (ASC) project, Sandia has acquired a set of advanced architecture test beds to help prepare applications and system software for the disruptive computer architecture changes that have begun to emerge and will continue to appear as HPC systems approach Exascale.  In contrast to ASC Advanced Technology or Commodity Technology supercomputer platforms, these test bed systems are not for production computing cycles.  Instead, they are intended to be pre-production or first-of-a-kind prototypes to support exploration of a diverse set of architectural alternatives that are possible candidates for future pre-Exascale systems.  While these test beds can be used for node-level exploration they also provide the ability to study inter-node characteristics to understand future scalability challenges.  To date, the test bed systems populate 1-6 racks and have on the order of 50-200 multi-core nodes, many with an attached co-processor or GP-GPU.

The test beds allow for path finding explorations of 1) alternative programming models, 2) architecture-aware algorithms, 3) energy efficient runtime and system software, 4) advanced memory sub-system development and 5) application performance. But that is not all.  Validation of computer architectural simulation studies can also be performed on these early examples of future Exascale platform architectures.  As proxy applications are developed and re-implemented in architecture-centric versions, the developers need these advanced architecture systems to explore how to adapt to an “MPI + X” paradigm, where “X” may be more than one disparate alternative.  This in turn, demands that tools be developed to inform the performance analyses.  ASC has embraced a co-design approach for its future advanced technology systems.  By purchasing from and working closely with the vendors on pre-production test beds, both ASC and the vendors are afforded early guidance and feedback on their paths forward.  This applies not only to hardware, but other enabling technologies such as system software, compilers, and tools.

There are currently several test beds available for use, with more in planning and integration phases. They represent distinct architectural directions and/or unique features important for future study. Examples of the latter are custom power monitors and on-node solid state disks (SSD).

Test Bed

Host Name
Cores per Accelerator /
40 Dual-Socket Intel Xeon Platinum None N/A Intel OmniPath Each processor core has dual AVX512 vector processing units that are FMA capable.
5 -only 2 w/ GPU Dual AMD EPYC 7401 AMD Radeon Instinct MI25 (@x per node) 64 nCU Compute units Mellanox FDR InfiniBand N/A
7 Fujitsu A64FX, 48 cores None N/A Mellanox EDR InfiniBand Fujitsu PRIMEHPC FX700

Armv8.2-A SVE instruction set
47 4) B0 ThunderX2

(43) A1 ThunderX2

All processors are 28 cores with 4 threads/core
None N/A Mellanox EDR InfiniBand
(with socket direct)
9 Five dual socket Intel IvyBridge with Xeon Phi co-processor and five Intel 24-core Cascade Lake nodes. Intel Xeon Phi
Co-processor (codenamed Knights Corner)
2 per node
Three with 57 1.1 GHz cores;
Two with 61 1.238 GHz cores
Mellanox Quad Data Rate InfiniBand Hetero testbed on restricted network

Dual IBM Power8, 10 cores


InfiniBand Other

 On restricted network; reduced access
56 Dual Intel Xeon Ivy Bridge 2.4 GHz, total 24 cores None N/A Aries Cray XC30m, Full featured RAS system including power monitoring and control capabilities
9 Dual IBM Power
8, 10 cores
NVIDIA K40 2 per node N/A Mellanox FDR IB Technology on the path to anticipated CORAL systems
10 Dual IBM Power
8, 10 cores
Dual NVIDIA Tesla V100 N/A Mellanox EDR IB Technology on the path to anticipated CORAL systems

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