ChISELS is a simulation code developed to model the etching and growth of semiconductor surfaces as they are processed to create micromachine devices (MEMS). ChISELS has its own WWW site with more details. See the "MultiMedia" page under that link for pictures of the adaptive gridding and level set tracking that the code performs in either 2d or 3d.
Larry Musson (lcmusso at sandia.gov) at Sandia is the lead developer for ChISELS. My contribution is in the algorithms and implementation of the parallel level set solver and associated octtree data structure used to store and track the surface as it evolves.
In a related effort, I worked with Craig Jorgensen and Rod Schmidt to create a parallel geometric modeler for MEMS designers. We used PVM (parallel virtual machine) to partition the modeling tasks geometrically into sub-pieces and distribute them across processors of a workstation cluster. This enabled large 3d models to be constructed from mask sets considerably more quickly.
Collaborators on these projects:
This paper describes ChISELS and its basic algorithms and application to semiconductor deposition processes commonly used for MEMS fabrication:
Feature Length-Scale Modeling of LPCVD and PECVD MEMS Fabrication Processes, L. C. Musson, P. Ho, S. J. Plimpton, R. C. Schmidt, Journal of Microsystems Technologies, 12, 137-142 (2005). (abstract) (pdf)
This conference paper describes the parallelization of the MEMS geometric modeler:
Development and Performance of a PVM Based Parallel Geometric Modeler for MEMS, C. Jorgensen, D. Melander, R. Schmidt, S. J. Plimpton, in Proc of Modeling and Simulation of Microsystems (MSM), Puerto Rico, April 2002, 218-221. (abstract) (pdf)