Publications

Abstract not provided.

Abstract not provided.

Goal was Assembly Test Chips (ATCs) which could be used for evaluating plastic encapsulation technologies. Circuits were demonstrated for measuring Au-Al wirebond and Al metal corrosion failure rates during accelerated temperature and humidity testing. The test circuits on the ATC02.5 chip were very sensitive to extrinsic or processing induced failure rates. Accelerated aging experiments were conducted with unpassivated triple track Al structures on the ATC02.6 chip; the unpassivated tracks were found to be very sensitive to particulate contamination. Some modifications to existing circuitry were suggested. The piezoresistive stress sensing circuitry designed for the ATC04 test chip was found suitable for determining the change in the state of mechanical stress at the die when both initial and final measurements were made near room temperature (RT). Attempt to measure thermal stress between RT and a typical polymer glass transition temperature failed because of excessive die resistor- substrate leakage currents at the high temperature end; suitable circuitry changes were developed to overcome this problem. One temperature and humidity experiment was conducted with Sandia developed static radom access memory parts to examine non-corrosion CMOS failures; this objective was not achieved, but corrosion failure at the metal to Si contacts on the die surface could be detected. This 2-year effort resulted in new designs for test circuits which could be used on an advanced ATC for reliability assessment in Defense Programs electronics development projects.

A new Assembly Test Chip, ATC04, designed to measure mechanical stresses at the die surface has been built and tested. This CMOS chip 0.25 in. on a side, has an array of 25 piezoresistive stress sensing cells, four resistive heaters and two ring oscillators. The ATCO4 chip facilitates making stress measurements with relatively simple test equipment and data analysis. The design, use, and accuracy of the chip are discussed and initial results are presented from three types of stress measurement experiments: four-point bending calibration, single point bending of a substrate with an ATC04 attached by epoxy, and stress produced by a liquid epoxy encapsulant.

Three dimensional multichip modules (MCMS) present an unusual challenge to the thermal designer. For example, high thermal resistance between upper planes of the MCM and the thermally anchored bottom plane can lead to the development of excessive temperatures. As new designs emerge, it becomes desirable to have methods of experimentally determining interior temperatures in the module in order to validate complex finite element calculations. In order to develop methods for assessing the thermal performance of a 3D MCM, we have developed a test module with three planes or slices. In this paper, we report on some initial calculations and measurements for the 3D MCM. In addition, we discuss the improvement in thermal performance obtained by replacing the top slice with a diamond substrate. Finite element method (FEM) thermal calculations have been done with both the workstation based analyzer P/Thermal from PDA Engineering and the PC program, Inertia from Modern Computer Aided Engineering. These analyses have assumed no heat losses by radiation or convection.

Short communication.

Two devices or tools are described which can be used to evaluate the ability of chip passivation or postbond coatings to protect a Si device from moisture penetration and resultant Al corrosion. The first device is a test chip with a number of Al triple track and other corrosion measurement structures. The authors present HAST data to illustrate the use of this chip in measuring failure rates and determining failure modes. The second device is a rugged, moisture sensitive, porous Si capacitor, which is compatible with high temperature passivation and postbond IC processing. Data are presented showing the stability of the device relative to that of an anodized Al moisture sensor and showing the variation of capacitance with moisture. Data are also presented showing that the capacitor can respond to a point source of water located over the porous region but remotely from the top electrode.

This report describes the features and use of the Sandia National Laboratories Assembly Test Chip Ver. 01 (ATC01). This chip contains a variety of Al conductor features which are intended for use in corrosion testing. These include triple tracks with a variety of line and gap widths, ladder structures, straight line structures, and van der Pauw sheet resistance structures. The chip is square, approximately 0.250 in. on a side, with a minimum Al feature size of 1.25 {mu}m. The various test structures on the die are described in detail and bonding layout data are given. Finally, we give an example of measurements made on ATC01 when packaged in a 40 lead CERDIP. 15 refs., 7 figs., 7 tabs.

A three generation family of CMOS silicon test chips for packaging diagnostics has been developed. These Assembly Test Chips (ATC) contain sensors that measure a number of variables associated with assembled IC degradation, including the degree of IC corrosion, handling damage, ESD threat, ppm, moisture, mechanical stress, mobile ion density, bond pad cratering, and high speed logic degradation. The ATC family are intended to give manufacturing feedback in four ways: direct feedback in evaluation of an Assembly Manufacturing Line in an objective, non-intrusive way; before and after comparisons on an assembly production line when an individual process, material, or piece of equipment has been changed; resident lifetime monitor for system package aging and ongoing reliability projection and thermal, mechanical, dc electrical, and high frequency mock-up evaluation of packaging (including multichip) schemes. 14 refs., 6 figs., 2 tabs.