Workshop on High-Consequence Control Verification
July 18, 2016 - Toronto, Ontario, Canada
In conjunction with the 28th International Conference on Computer Aided Verification (venue and registration information will be available at the CAV website).
Paper submission (6 pages maximum): April 7, 2016 April 21, 2016 (final extension)
Notification: May 12, 2016
Final version: June 9, 2016
Workshop: July 18, 2016
The Workshop on High-Consequence Control Verification (HCCV) focuses on formal methods concepts and techniques to ensure the highest levels of reliability, safety, and security for digitally controlled devices, including the effects of possibly extreme physical environments. The workshop targets applications where the severe consequences of failure justify extraordinary investments not appropriate for less critical devices – including special methodologies at the design stage to enable verifying stringent reliability, safety, and security requirements in the resulting devices under both nominal and out-of-nominal (fault) conditions. Such needs exist in domains including defense, medical devices, and scientific instrumentation.
The willingness to make greater investments for small but high-consequence devices can provide an opportunity to leverage emerging, more powerful formal methods techniques that may currently be considered too costly for “mainstream” industrial applications. Novel ideas for design and analysis techniques that promote in-depth verifiability are of strong interest for these high-consequence digital controllers. The HCCV workshop offers a new forum for engagement among formal methods researchers, tool developers, and practitioners.
Topics of interest include:
- Theory and techniques for formally verified high-consequence digital design (via model checking and/or theorem proving), such as:
- Correct-by-construction synthesis
- Exhaustive or probabilistic analysis of fault consequences
- Incorporation of analog physics
- Applications to safety-critical digitally controlled devices in domains such as:
- Supervisory control and data acquisition (SCADA)
- Submissions should target requirements for high-consequence devices, not general-purpose software verification or cybersecurity.
- Submissions should target mathematical analyzability of designs, not merely testing- and simulation-based verification or the use of standard electronic design automation (EDA) tools.
Papers of up to 6 pages, as PDF generated by LaTeX using EasyChair format, should be submitted through EasyChair on or before April 21, 2016. Submitted papers must represent original work and will be peer-reviewed. Each accepted paper will be allotted an approximately 25-minute speaking slot. The collection of accepted papers will be made available for download from the workshop website.
Jackson R. Mayo (co-chair)
Sandia National Laboratories
Livermore, California, United States
Michael J. Butler (co-chair)
University of Southampton, United Kingdom