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Publication	Type	Year
Polynomial Preconditioning with the GMRES Polynomial Householder Symposium 2022 Jennifer Ann Loe, Ronald Morgan, Mark Embree, Erik Gunnar Boman, Heidi K. Thornquist	Conference Presentation – 2022 Conference Presentation	2022
Xyce Circuit Simulator and Surrogate Modeling DARPA Microelectronics Access Design Automation Meeting Eric R. Keiter, Jason Verley, Heidi K. Thornquist, Paul Allen Kuberry, Edgar Galvan	Display or Poster (non-conference) – 2022 Display or Poster (non-conference)	2022
Trilinos User Group Meeting Solvers Update Trilinos User Group Meeting Sivasankaran Rajamanickam, Alexander Heinlein, Heidi K. Thornquist, Ichitaro Yamazaki	Conference Presentation – 2021 Conference Presentation	2021
Xyce Circuit Simulator and Surrogate Modeling DARPA Electronics Resurgence Initiative (ERI) Summit & Microsystems Technology Office (MTO) Symposium Eric R. Keiter, Jason Verley, Heidi K. Thornquist, Paul Allen Kuberry, Edgar Galvan	Conference Poster – 2021 Conference Poster	2021
Polynomial Preconditioned GMRES in Trilinos: Practical Considerations for High Performance Computing SIAM Parallel Processing 2020 Jennifer Ann Loe, Heidi K. Thornquist, Erik Gunnar Boman https://www.osti.gov/search/identifier:1765637	Conference Paper – 2020 Conference Paper	2020
Polynomial Preconditioned GMRES in Trilinos: Practical Considerations for High-Performance Computing SIAM Conf. on Parallel Processing Jennifer Loe, Heidi K. Thornquist, Erik Gunnar Boman https://www.osti.gov/search/identifier:1643432	Conference Paper – 2019 Conference Paper	2019
Polynomial Preconditioning for Avoiding Communication in GMRES Preconditioning 2019 Jennifer Ann Loe, Heidi K. Thornquist, Erik Gunnar Boman https://www.osti.gov/search/identifier:1641026	Conference Paper – 2019 Conference Paper	2019
Basker: Parallel Sparse LU Factorization utilizing Hierarchical Parallelism and Data Layouts Journal of Parallel Computing Joshua Dennis Booth, Nathan David Ellingwood, Heidi K. Thornquist, Sivasankaran Rajamanickam https://www.osti.gov/search/identifier:1499033	Journal Article – 2019 Journal Article	2019
Polynomial Preconditioned GMRES for Communication Reduction The Fifteenth Copper Mountain Conference on Iterative Methods Heidi K. Thornquist, Jennifer A. Loe, Heidi K. Thornquist, Erik Gunnar Boman https://www.osti.gov/search/identifier:1592317	Conference Paper – 2018 Conference Paper	2018
Using the Basker Linear Solvers in Xyce Trilinos User Group Meeting Heidi K. Thornquist, Ting Mei, Sivasankaran Rajamanickam, Nathan David Ellingwood https://www.osti.gov/search/identifier:1491763	Conference Paper – 2018 Conference Paper	2018
Basker : A Threaded Sparse LU factorization utilizing Hierarchical Parallelism and Data Layouts International Workshop on Accelerators and Hybrid Exascale Systems (IPDPS 2016) Sivasankaran Rajamanickam, Heidi K. Thornquist, Joshua Booth https://www.osti.gov/search/identifier:1484926	Conference Paper – 2017 Conference Paper	2017
Multithreaded Sparse LU Factorization utilizing Hierarchical Parallelism and Data Layouts Journal of Parallel Computing Sivasankaran Rajamanickam, Joshua Booth, Heidi K. Thornquist	Journal Article – 2016 Journal Article	2016
Robust Solvers for Circuit Simulation on Modern Architectures 2016 Cis Erb Sivasankaran Rajamanickam, Joshua Booth, Heidi K. Thornquist https://www.osti.gov/search/identifier:1530033	Display or Poster (non-conference) – 2016 Display or Poster (non-conference)	2016
Basker: A Threaded Sparse LU Factorization Utilizing Hierarchical Parallelism and Data Layouts The Sixth International Workshop on Accelerators and Hybrid Exascale Systems (IPDPS workshop) Joshua Dennis Booth, Sivasankaran Rajamanickam, Heidi K. Thornquist https://www.osti.gov/search/identifier:1347159	Conference Paper – 2016 Conference Paper	2016
ShyLU and Thread Scalable Subdomain Solvers Trilinos User Group Meeting Sivasankaran Rajamanickam, Erik Gunnar Boman, Andrew Michael Bradley, Joshua Dennis Booth, Mehmet Deveci, Kyungjoo Kim, Clark R. Dohrmann, Heidi K. Thornquist, Edmond Chow, Aftab Patel https://www.osti.gov/search/identifier:1514218	Presentation (non-conference) – 2015 Presentation (non-conference)	2015
Basker: A Threaded Sparse LU Factorization Utilizing Hierarchical Parallelism and Data Layouts IEEE International parallel and distributed processing symposium Joshua Dennis Booth, Sivasankaran Rajamanickam, Heidi K. Thornquist https://www.osti.gov/search/identifier:1332050	Conference Paper – 2015 Conference Paper	2015
Installing the Anasazi eigensolver package with application to some graph eigenvalue problems Richard B. Lehoucq, Erik Gunnar Boman, Karen D. Devine, Heidi K. Thornquist, Nicole Slattengren https://www.osti.gov/search/identifier:1494630	SAND Report – 2014 SAND Report	2014
Xyce Parallel Electronic Simulator Users' Guide, Version 6.0.1 Gary J. Denison, Ting Mei, Thomas V. Russo, Richard Schiek, Heidi K. Thornquist, Jason Verley, Debora A. Fixel, Todd S. Coffey, Roger P. Pawlowski, Christina E. Warrender, David G. Baur https://www.osti.gov/search/identifier:1147554	SAND Report – 2014 SAND Report	2014
Xyce Parallel Electronic Simulator Reference Guide, Version 6.0.1 Gary J. Denison, Ting Mei, Thomas V. Russo, Roger P. Pawlowski, Richard Schiek, Todd S. Coffey, Heidi K. Thornquist, Jason Verley, Christina E. Warrender, Debora A. Fixel, David G. Baur https://www.osti.gov/search/identifier:1147677	SAND Report – 2014 SAND Report	2014
Assessing the Role of Mini-Applications in Predicting Key Performance Characteristics of Scientific and Engineering Applications Elsevier Journal of Parallel and Distributed Computing Richard Frederick Barrett, Paul Crozier, Douglas W. Doerfler, Michael A. Heroux, Paul Lin, Heidi K. Thornquist, Timothy G. Trucano, Courtenay T. Vaughan https://www.osti.gov/search/identifier:1121689	Journal Article – 2013 Journal Article	2013
Xyce Parallel Electronic Simulator Users' Guide, Version 6.0 Cynthia Ann Phillips, Ting Mei, Eric R. Keiter, Richard Schiek, Heidi K. Thornquist, Jason Verley, Todd S. Coffey, Roger P. Pawlowski, Christina E. Warrender, Debora A. Fixel, David G. Baur https://www.osti.gov/search/identifier:1096496	SAND Report – 2013 SAND Report	2013
Xyce Parallel Electronic Simulator Reference Guide, Version 6.0 Gary J. Denison, Ting Mei, Thomas V. Russo, Roger P. Pawlowski, Richard Schiek, Todd S. Coffey, Heidi K. Thornquist, Jason Verley, Christina E. Warrender, Debora A. Fixel, David G. Baur https://www.osti.gov/search/identifier:1096463	SAND Report – 2013 SAND Report	2013
Scalable Transistor-Level Circuit Simulation for Radiation Effects Prediction CIS External Review Heidi K. Thornquist https://www.osti.gov/search/identifier:1661124	Other Publication – 2013 Other Publication	2013
Xyce Parallel Electronic Simulator Release Notes 5.1.2 Gary J. Denison, Robert J. Hoekstra, Thomas V. Russo, Richard Schiek, Ting Mei, Heidi K. Thornquist, Roger P. Pawlowski, Todd S. Coffey, Eric L. Rankin, Deborah A. Fixel, Keith R Santarelli https://www.osti.gov/search/identifier:1097210	SAND Report – 2013 SAND Report	2013
Xyce Parallel Electronic Simulator Reference Guide, Version 5.1.2 Gary J. Denison, Thomas V. Russo, Richard Schiek, Ting Mei, Heidi K. Thornquist, Todd S. Coffey, Keith R Santarelli, Roger P. Pawlowski, Eric L. Rankin, Deborah A. Fixel https://www.osti.gov/search/identifier:1097213	SAND Report – 2013 SAND Report	2013
Document Title	Type	Year

Results 1–25 of 66

Publications

Polynomial Preconditioning with the GMRES Polynomial

Xyce Circuit Simulator and Surrogate Modeling

Trilinos User Group Meeting Solvers Update

Xyce Circuit Simulator and Surrogate Modeling

Polynomial Preconditioned GMRES in Trilinos: Practical Considerations for High Performance Computing

Polynomial Preconditioned GMRES in Trilinos: Practical Considerations for High-Performance Computing

Polynomial Preconditioning for Avoiding Communication in GMRES

Basker: Parallel Sparse LU Factorization utilizing Hierarchical Parallelism and Data Layouts

Polynomial Preconditioned GMRES for Communication Reduction

Using the Basker Linear Solvers in Xyce

Basker : A Threaded Sparse LU factorization utilizing Hierarchical Parallelism and Data Layouts

Multithreaded Sparse LU Factorization utilizing Hierarchical Parallelism and Data Layouts

Robust Solvers for Circuit Simulation on Modern Architectures

Basker: A Threaded Sparse LU Factorization Utilizing Hierarchical Parallelism and Data Layouts

ShyLU and Thread Scalable Subdomain Solvers

Basker: A Threaded Sparse LU Factorization Utilizing Hierarchical Parallelism and Data Layouts

Installing the Anasazi eigensolver package with application to some graph eigenvalue problems

Xyce Parallel Electronic Simulator Users' Guide, Version 6.0.1

Xyce Parallel Electronic Simulator Reference Guide, Version 6.0.1

Assessing the Role of Mini-Applications in Predicting Key Performance Characteristics of Scientific and Engineering Applications

Xyce Parallel Electronic Simulator Users' Guide, Version 6.0

Xyce Parallel Electronic Simulator Reference Guide, Version 6.0

Scalable Transistor-Level Circuit Simulation for Radiation Effects Prediction

Xyce Parallel Electronic Simulator Release Notes 5.1.2

Xyce Parallel Electronic Simulator Reference Guide, Version 5.1.2