Sandia National Laboratories

Richard C. Murphy

Senior Member of Technical Staff
Scalable Computer Architecture Department
Sandia National Laboratories
PO Box 5800, MS-1319
Albuquerque, NM 87185-1319

Office: CSRI/322
Phone: 505-844-7122
Fax: 505-845-7442
email:rcmurph@sandia.gov

I am a computer architect at Sandia National Laboratories. I received my Ph.D. in computer engineering at the University of Notre Dame, under the direction of Peter Kogge. My research interests include computer architecture, with a focus on memory systems and Processing-In-Memory, VLSI, and massively parallel architectures, programming languages, and runtime systems. I spent 2000 to 2002 at Sun Microsystems focusing on hardware resource management and dynamic configuration.

Education

Industry Experience

Research Interests

  • Processing-In-Memory (PIM)
  • Multithreaded Computer Architecture
  • Prediction and Modeling
  • Programming Languages and Compilers
  • Associative Memory Neural Networks

Honors and Awards

  • Kaneb Center Outstanding Graduate Student Instructor (CSE321, Fall 2002)
  • Outstanding Teaching Assistant (CSE322, Spring 1999)
  • John J. Reilly Scholar (1998)

Patents and Disclosures

  • Underwood, Keith D., Arun F. Rodrigues, Peter M. Kogge, and Richard C. Murphy Intra-Cache Line Gather/Scatter, Submitted to the USPTO 2/12/2008.
  • Murphy, Richard C., Scott Carter, Shrikant Deshpande, and Mario Ornelas. System and Method for Dynamic Resource Reconfiguration Using a Dependency Graph. US Patent 7,152,157, granted December 19, 2006.
  • Murphy, Richard C. Automated Resource Management Using Perceptron Prediction. US Patent 7,191,329, granted March 13, 2007.

Refereed Journal Papers

Refereed Conference and Workshop Papers

Invited Talks

  • DOE's Institute for Advanced Architecture and Algorithms: an Application-Driven Approach, SciDAC 2009, June 14-18, San Diego, CA.
  • Data Movement Dominates: An Application-Centric View of High Performance Interconnects, HSD 2009 20th Annual Workshop on Interconnects within High Speed Digital Systems, May 3-6, 2009, Santa Fe, NM.
  • Can We Continue to Build Supercomputers Out of Processors Optimized for Laptops?, 13th Workshop on Distributed Supercomputing (SOS 13), March 9-12, 2009, Hilton Head, SC.
  • Initial Thoughts on Cortex Scale Supercomputer Simulations, DARPA Electronic Cortex Workshop, August 2, 2007.
  • Traveling Threads: A New Multithreaded Execution Model, Oak Ridge National Lab, December 6, 2005.
  • Traveling Threads: A New Multithreaded Execution Model, Sandia National Lab, April 11, 2005.
  • Processing-In-Memory: Technology, Execution Model, Architecture, and Traveling Threads, 2003 Conference on High-Speed Computing (LANL/LLNL/SNL), Salishan Lodge, Gleneden Beach, OR., April 21-24 2003

Teaching

  • University of Notre Dame, Computer Architecture I, Fall 2002 and 2003.
Contact | Map | Privacy and Security