Sandia has developed a structured Application Specific Integrated Circuit (ASIC) that enables rapid turn-around, lowers non-recurring engineering (NRE) and development costs, and reduces development risk by using pre-qualified base arrays. The structured ASIC is a metal-via configurable, regular fabric like structure using the ViASIC® Via-Mask Technology. Sandia’s structured ASIC is partitioned for power sequencing and redundancy which also allows unused transistors to be turned off to minimize power consumption, static current, and photocurrent. The option to include on-package decoupling capacitors is also included. Currently, two product platforms have been developed.
Features:
- 285K ASIC gate-equivalent
- 380Kb configurable distributed Dual-Port RAM
- 368Kb configurable ROM
- 239 configurable I/Os, PCI compatible
- 8 pairs LVDS I/Os
- Dual Oscillators
- Power Monitor Circuit
- Phase Lock Loop
- 4 Power partitions
- Unused circuits totally isolated
- Package options
- 400 pin plastic LGA
- Ceramic version of 400 LGA in development
- 391 pin ceramic PGA
- Other
- 3.3v, 0.35um, CMOS-SOI, Radiation-Hardened
Whistler ViArray Mixed-Signal RH Structured ASIC
Features:
- ~246K ASIC gate-equivalent
- ~328Kb configurable distributed Dual-Port RAM
- ~320Kb configurable ROM
- 239 configurable I/Os, PCI compatible
- 8 pairs LVDS I/Os
- Analog Features
- Oscillators
- Power supply monitors
- Phase locked loop
- Band gap reference
- A-D converter
- D-A converter
- Analog muxes
- Amplifiers
- Comparators
- Sample and hold
- 4 Power partitions
- Unused circuits totally isolated
- Package options
- 400 pin plastic LGA
- Ceramic version of 400 LGA in developmentRE: More changes to external web site.
- 391 pin ceramic PGA
- Other
- 3.3v, 0.35um, CMOS-SOI, Radiation-Hardened
For additional information or questions, please email us at ASIC Custom Solutions.
