Ion Trap Fabrication
In developing our ion traps, particular emphasis was placed on the design principle of minimizing the line of sight access to the ion from exposed dielectrics, thereby reducing the impact of stray electric charges. To realize this design principle, the top metal layer of these traps (comprising electrodes, their leads, and outside grounded regions) overhang their supporting oxide pillars by 5 μm (a). The oxide pillars are grown through multiple layers of plasma enhanced chemical vapor deposition, and are between 9 and 14 μm thick. The overhang distance is a controllable value achieved by using vertical etch stops around the pillars. The overhang allows for vertical deposition of metal on top of the aluminum electrode layer without shorting DC control or RF electrodes. The lateral separation between electrically isolated top metal layers (such as between neighboring electrodes) is set to be 7 microns, and the lateral dimensions of the electrodes can be arbitrarily determined.
A hole through the Si substrate of the trap chip (b) runs the entire length of the trapping region to allow for loading of ions from the backside of the trap (preventing shorting of the trap electrodes by the atoms, which can occur when loading ions from the side). DC rails inside the RF rails allow for additional principle axis rotation and compensation. The back side of the chip is evaporated with gold at a small off-normal angle to coat the exposed vertical edges of the silicon substrate and the platform which supports the electrodes. This prevents charge buildup by pinning the backside of the chip to ground.